Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2001-08-29
2003-07-29
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S678000, C257S685000, C257S690000, C257S692000, C257S734000, C257S773000, C257S774000, C257S777000, C257S784000, C257S737000, C257S738000
Reexamination Certificate
active
06600221
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device comprising a plurality of stacked semiconductor chips.
2. Description of the Related Art
FIG. 2
shows a semiconductor device disclosed in the unexamined Japanese Patent Publication (KOKAI) No. 10-84076.
As shown in
FIG. 2
, the semiconductor device comprises a small chip
10
, a large chip
20
, a wiring board
30
having an inner terminal
33
and an outer terminal
36
connected to the inner terminal
33
via an electric wire
38
, and an auxiliary frame
40
having a chip-side terminal
43
and a board-side terminal
46
connected to the chip-side terminal
43
using a connecting member
47
. The small chip
10
is disposed on a central portion of the wiring board
30
. An electrode pad
13
of the small chip
10
is connected to the inner terminal
33
of the wiring board
30
via a solder ball
14
. The auxiliary frame
40
is engaged to the outer part of the small chip
10
. An electrode pad
46
of the auxiliary frame
40
is connected to the inner terminal
33
of the wiring board
30
via a solder ball
48
. The large chip
20
is superposed on the small chip
10
and the auxiliary frame
40
, and an electrode pad
23
of the large chip
20
is connected to the chip-side terminal
43
of the auxiliary frame
40
via a solder ball
24
.
According to this semiconductor device, however, the board
30
and the large chip
20
are connected to each other using the auxiliary frame
40
, and since it is difficult to fabricate the auxiliary frame
40
, the auxiliary frame
40
is expensive. Further, in this semiconductor device, since the connecting force between the chip and the board is great, it is difficult to release a thermal stress between the board and the chip generated based on a difference in coefficient of thermal expansion between the board and the chip, and there is a defect that a reliability of a temperature cycle is low.
In the case of a lamination type semiconductor device in which semiconductor chips
71
,
72
and
73
are sequentially stacked on aboard
70
shown in
FIG. 3
, it is necessary to provide the board
70
with through holes
74
. Therefore, there is a defect that the manufacturing cost of the board
70
becomes high.
SUMMARY OF THE INVENTION
Thereupon, it is an object of the present invention to provide a new, reliable and inexpensively produced semiconductor device in which the above-described defects of the prior art are overcome, a difference in coefficient of thermal expansion between a board and chip is absorbed.
To achieve the above object, the present invention basically employs the following technique.
That is, the present invention provides a semiconductor device having a substrate on which a plurality of semiconductor chips are stacked, wherein the semiconductor device comprising; a first semiconductor chip mounted on the substrate, a plurality of second semiconductor chips size of which are larger than that of the first semiconductor chip and stacked on the first semiconductor chip with a size-increasing order, a bonding pad formed on the semiconductor chip, a circuit pattern formed on the substrate, a bonding wire for connecting the bonding pad formed on the semiconductor chip and the circuit pattern formed on the substrate, a through hole, formed on the substrate, through which the bonding wire is to be inserted, and further wherein the bonding wire is wired so as to be substantially perpendicularly to a surface of the semiconductor chip.
With this structure, since a thermal stress generated based on a difference in coefficient of thermal expansion between the board and the chip is small, a reliability of the semiconductor chip is enhanced, and the semiconductor chip can be fabricated inexpensively.
REFERENCES:
patent: 6294839 (2001-09-01), Mess et al.
patent: 6333211 (2001-12-01), Sato et al.
patent: 6337226 (2002-01-01), Symons
patent: 09139441 (1997-05-01), None
patent: 10-084076 (1998-03-01), None
patent: 10144851 (1998-05-01), None
patent: 11111758 (1999-04-01), None
Flynn Nathan J.
Greene Pershelle
Katten Muchin Zavis & Rosenman
NEC Electronics Corporation
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