Semiconductor device with stacked memory and processor LSIs

Details Semiconductor device with stacked memory and processor LSIs Semiconductor device with stacked memory and processor LSIs

2009-05-14

2010-11-16

Soward, Ida M (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S685000, C257S723000, C257S777000, C257SE25021, C257SE25027, C257SE27137, C257SE27144, C257SE27161

Reexamination Certificate

active

07834440

ABSTRACT:
In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI100and a memory LSI200are stacked and the processor LSI100and the memory LSI200in the same combination are stacked adjacent to each other in the vertical direction. Communication between the processor LSI100and the memory LSI200in the same combination is performed by a dedicated electrode provided therebetween, and communication between processor LSIs100and communication from the processor LSI100to the outside are performed by a through silicon via for signal11which passes through all the LSIs.

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