Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1998-07-02
2002-02-26
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S244000, C327S276000
Reexamination Certificate
active
06351166
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices, and particularly relates to a semiconductor device equipped with a timing-stabilization circuit such as a DLL (delay-locked loop) circuit.
2. Description of the Related Art
Some semiconductor devices control a timing of a clock signal by use of a DLL circuit or the like.
FIG. 1
is a block diagram of a configuration in which a DLL circuit is used as a timing-stabilization circuit for data-output operations.
The configuration of
FIG. 1
includes an output circuit
501
, a variable-delay circuit
502
, an ESD-protection circuit
503
, an input circuit
504
, a frequency divider
505
, a phase-comparison circuit
506
, a delay-control circuit
507
, a variable-delay circuit
508
, a dummy-input circuit
509
, a dummy-output circuit
510
, a dummy-output load
511
, and a dummy-ESD-protection circuit
512
.
An external clock signal CLK input to an input node is supplied to the input circuit
504
via the ESD-protection circuit
503
. The input circuit
504
is comprised of a current-mirror circuit or the like. The input circuit
504
generates an internal-clock signal i-clk based on the external clock signal CLK supplied thereto. The internal-clock signal i-clk is delayed by the variable-delay circuit
502
by an appropriate delay amount, and is supplied to the output circuit
501
. The output circuit
501
uses the internal-clock signal i-clk having the appropriate delay amount as a synchronization signal so as to latch data. The latched data is then supplied from the output circuit
501
to an exterior of the semiconductor device via an output node.
The signal path from the input node to the output node inevitably introduces a delay which is inherent to the circuit, so that the data output to the exterior of the device has a timing determined by the delay inherent to the circuit. In order to ensure that the data output to the exterior of the device is adjusted to have a predetermined timing relation with the external clock signal CLK, a DLL circuit mainly comprised of the phase-comparison circuit
506
, the delay-control circuit
507
, the variable-delay circuit
508
, and the variable-delay circuit
502
is employed.
The internal-clock signal i-clk is subjected to frequency division in the frequency divider
505
to generate a dummy-clock signal d-clk and a reference-clock signal c-clk having the same phase as the dummy-clock signal d-clk. The dummy-clock signal d-clk is supplied to the variable-delay circuit
508
. The variable-delay circuit
508
is controlled to delay the dummy-clock signal d-clk by the same delay amount as that applied by the variable-delay circuit
502
. The dummy-clock signal d-clk delayed by the variable-delay circuit
508
is then supplied to the phase-comparison circuit
506
via the dummy-output circuit
510
, the dummy-output load
511
, the dummy-ESD-protection circuit
512
, and the dummy-input circuit
509
. Here, the dummy-output circuit
510
has the same delay characteristics as the output circuit
501
, and the dummy-output load
511
emulates the output load of the device. Further, the dummy-ESD-protection circuit
512
has the same delay characteristics as the ESD-protection circuit
503
, and the dummy-input circuit
509
has the same delay characteristics as the input circuit
504
.
The phase-comparison circuit
506
makes a comparison of the reference-clock signal c-clk with the clock signal supplied from the dummy-input circuit
509
. To ensure that both clock signals have the same phase, the phase-comparison circuit
506
controls the delay amount of the variable-delay circuit
508
via the delay-control circuit
507
. In this manner, the clock signal output from the dummy-output circuit
510
is adjusted so as to have a predetermined timing relation with the external clock signal CLK.
A total delay of the ESD-protection circuit
503
, the input circuit
504
, the variable-delay circuit
502
, and the output circuit
501
is equal to a total delay of the dummy-ESD-protection circuit
512
, the dummy-input circuit
509
, the variable-delay circuit
508
and the dummy-output circuit
510
. Because of this, the data output from the output circuit
501
to the exterior of the device ends up having the predetermined timing relation with the external clock signal CLK.
In this configuration, even when the characteristics of the ESD-protection circuit
503
, the input circuit
504
, the variable-delay circuit
502
, and the output circuit
501
are changed due to variations in a power voltage and/or temperature, the characteristics of the dummy-ESD-protection circuit
512
, the dummy-input circuit
509
, the variable-delay circuit
508
, and the dummy-output circuit
510
also change in the same manner. Because of this, the data output from the output circuit
501
to the exterior of the device always keeps the same timing relation with the external clock signal CLK regardless of a power-voltage variation and/or a temperature variation.
The frequency divider
505
divides a frequency of the internal-clock signal i-clk by N so as to generate the dummy-clock signal d-clk and the reference-clock signal c-clk. The phase-comparison circuit
506
thus makes a phase comparison once in every N cycles, thereby attending to timing adjustment. In the semiconductor device having the configuration of
FIG. 1
, the DLL circuit is always in operation, so that the timing adjustment is performed in every N cycles even during a data-output operation.
When data is output from an output circuit, in general, it is necessary to drive the output load attached to the output node. Because of this, the output circuit consumes a large amount of an electric current at an instance when the data is output, thereby generating a huge noise in an internal power voltage of the semiconductor device. When the internal power voltage suffers a huge noise, a series of dummy circuits including the variable-delay circuit
508
create a fluctuation in a signal timing as a signal passes therethrough. As a consequence, a clock signal t-clk, which is supplied from the dummy-input circuit
509
for a phase comparison by the phase-comparison circuit
506
, ends up having an undesirable timing displacement.
FIGS. 2A through 2G
are timing charts for explaining a problem caused by a power-voltage noise at a time of a data-output operation.
FIGS. 2A through 2G
show the internal-clock signal i-clk, a read-enable signal, a data signal appearing at the output node, a ground voltage GND, the clock signal t-clk output from the dummy-input circuit
509
, the reference-clock signal c-clk, and a clock signal observed at nodes N
1
and N
2
of
FIG. 1
, respectively.
As shown in the figures, when data D
1
is output from the output node as the read-enable signal is supplied to the semiconductor device, the load is imposed on the output circuit
501
, thereby creating a spike noise S
1
in the power voltage (ground voltage GND). The noise S
1
in the power voltage results in a timing of a rising edge being displaced with respect to a clock pulse P
1
of the clock signal t-clk. If a pulse of the reference-clock signal c-clk that is supplied once in every N cycles happens to appear with the displaced clock pulse P
1
, a phase adjustment of the DLL circuit is performed in accordance with the displaced clock pulse P
1
, thereby changing the delay amount of the variable-delay circuit
502
and the variable-delay circuit
508
. As a result, the clock signal appearing at the nodes N
1
and N
2
ends up having an erroneous timing which is caused by the displaced clock pulse P
1
. Data D
2
output at the output node, therefore, appears at a wrong timing indicated by solid lines in
FIG. 2C
rather than at a correct timing shown by dashed lines.
In general, a fluctuation in the power voltage is compensated for by a timing adjustment which the DLL circuit performs. In order for such a timing adjustment to be effective, however, the power voltage should remain at a given voltage after changing
Callahan Timothy P.
Englund Terry L.
Fujitsu Limited
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