Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device
Reexamination Certificate
2001-08-31
2003-12-02
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
Having specific type of active device
C257S904000, C257S903000, C257S221000, C365S154000, C365S156000
Reexamination Certificate
active
06657243
ABSTRACT:
Japanese Patent Application No. 2000-266794, filed Sep. 4, 2000, is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Filed of the Invention
The present invention relates to a semiconductor device including a semiconductor memory device such as a static random access memory (SRAM).
2. Related Art
An SRAM is one type of semiconductor memory device and does not need refreshing. Therefore, the SRAM enables the system configuration to be simplified and consumes only a small amount of electric power. Because of this, the SRAM is suitably used as a memory for portable devices such as portable telephones.
There has been a demand for miniaturization of portable devices. To deal with this demand, the size of an SRAM section in which a memory cell array of the SRAM is formed must be reduced.
SUMMARY OF THE INVENTION
An objective of the present invention is to provide a semiconductor device which can be reduced in size.
(1) According to the present invention, there is provided a semiconductor device provided with an SRAM section which includes a plurality of memory cells, wherein:
each of the memory cells comprises a first well of a primary conductivity type, a second well of a secondary conductivity type, a first load transistor, a second load transistor, a first driver transistor, a second driver transistor, a first access transistor, and a second access transistor;
the first and second load transistors are located on the first well;
the first and second driver transistors and the first and second access transistors are located on the second well;
the semiconductor device comprises a third well of the primary conductivity type;
a bottom section of the third well is located at a position deeper than bottom sections of the first and second wells; and
the third well is connected to the first well in each of the memory cells.
In the case of forming an interconnect for supplying a potential to the first well in which the load transistors are disposed on the semiconductor substrate, a well contact region in which the interconnect is connected to the first well must be formed on a semiconductor substrate. This hinders miniaturization of the SRAM section. According to the present invention, the third well becomes an interconnect for connecting the first well. This enables the SRAM section to be miniaturized.
Since the third well is disposed over the entire area of the memory cell region in the SRAM section, the well resistance of the first well can be decreased. Therefore, according to the present invention, occurrence of the latchup caused by an increase in the well resistance can be prevented.
According to the present invention, the third well of the primary conductivity type can be disposed under the second well of the secondary conductivity type in the form of a buried layer. A reverse biased pn junction is formed between the second well and the third well. A reverse biased pn junction is also formed between the second well and drains (for example, drain diffusion region of driver transistor) formed on the second well. In the case where a depletion layer in the pn junction is distorted due to funneling when &agr;-rays are incident on the drain on the second well, the third well functions as a guard band. Specifically, the amount of funneling charge flowing into the drains on the second well can be limited to the extent of the depth of the second well. Therefore, in the present invention, occurrence of soft errors due to &agr;-rays can be prevented.
(2) The semiconductor device of the present invention may further comprise a semiconductor circuit section, wherein:
the semiconductor circuit section comprises a fourth well of the primary conductivity type; and
the fourth well is connected to the third well.
According to this configuration, a potential can be supplied to the first well from the fourth well through the third well.
(3) In the semiconductor device of the present invention,
the SRAM section may have no well contact region in the third well.
According to this configuration, the SRAM section can be miniaturized.
(4) In the semiconductor device of the present invention,
the SRAM section may have a well contact region in the third well.
According to this configuration, the well resistance of the first well can be decreased. In particular, substrate current generated in the fourth well can be prevented from flowing into the memory cell region by disposing the well contact region at the boundary between the fourth well and the third well. This further improves latchup withstand capacity.
(5) In the semiconductor device of the present invention,
the SRAM section may include a normal memory cell group and a redundant memory cell group; and
the normal memory cell group may be able to be replaced by the redundant memory cell group.
According to this configuration, the yield of the SRAM section can be improved.
(6) In the semiconductor device of the present invention,
each of the memory cells may have a power supply line for a cell;
the power supply line for a cell may supply a potential to the first and second load transistors in each of the memory cells;
the power supply line for a cell may be electrically isolated from the third well;
each of the normal and redundant memory cell groups may have a power supply line for a memory cell group;
the power supply line for a memory cell group may supply a potential to the power supply lines for a cell in each of the normal and redundant memory cell groups;
the power supply line for a memory cell group may include a power supply disconnecting circuit; and
the power supply line for a cell may be able to be disconnected from a power supply by the power supply disconnecting circuit.
According to this configuration, the power supply disconnecting circuit is provided to the power supply line for a memory cell group. Therefore, in the case where abnormal current flows into a certain memory cell through the power supply line for a memory cell group and the power supply line for a cell, the following countermeasures can be taken. The memory cell group including such a defective memory cell is replaced by the redundant memory cell group. The power supply line for a cell in the memory cell group including the defective memory cell is disconnected from the power supply by the power supply disconnecting circuit. This prevents current from flowing into the defective memory cell through the power supply line for a memory cell group and the power supply line for a cell. Therefore, it is possible to reduce the current defects in the memory cell, whereby the yield can be improved.
Moreover, the power supply line for a cell is disconnected from the power supply by using a memory cell group as one unit. Therefore, the area of the SRAM section can be decreased in comparison with the case of using the power supply line for a cell as one unit.
In addition, since the third well is isolated from the power supply line for a cell, current flowing into the defective memory cell through the third well can be prevented. Therefore, it is possible to reduce the current defects by only disconnecting the power supply line for a cell.
(7) In the semiconductor device of the present invention,
the power supply line for a memory cell group may supply a potential to a bit-line precharge circuit for each of the memory cells; and
the bit-line precharge circuit may be able to be disconnected from a power supply by the power supply disconnecting circuit.
According to this configuration, the bit line precharge circuit is connected to the power supply line for a memory cell group. Therefore, in the case where abnormal current flows into a certain memory cell through the bit line precharge circuit, the following countermeasures can be taken. The memory cell group including such a defective memory cell is replaced by the redundant memory cell group. The bit line precharge circuit is disconnected from the power supply. This prevents current from flowing into the defective memory cell through the bit line precharge circuit. Therefore, it is possible to reduce the
Kodaira Satoru
Kumagai Takashi
Noda Takafumi
Takeuchi Masahiro
Dickey Thomas L
Hogan & Hartson LLP
Tran Minh Loan
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