Semiconductor device with specifically oriented control layer

Details Semiconductor device with specifically oriented control layer Semiconductor device with specifically oriented control layer

1985-05-03

1987-03-17

Clawson, Jr., Joseph E.

357 22, 357 36, 357 60, 357 89, H01L 2974

Patent

active

046511881

ABSTRACT:
In manufacturing a GTO, a silicon wafer is cut away along one of the crystal planes indicated by {n11} in Miller indices, and the burried gate or the current channels are so arranged on the crystal plane that at least one longitudinal direction thereof is substantially in parallel with at least one of axes indicated by <2nn> on condition that the inner product of the plane vector and the axis vector is zero. In the GTO thus manufactured, it is possible to minimize the crystal defect density on the crystal plane and thus to realize the GTOs having uniform turned-on voltage, in particular, while increasing the controllable current markedly.

REFERENCES:
patent: 3798513 (1974-03-01), Ono
patent: 3821783 (1974-06-01), Sugita et al.
patent: 3999211 (1976-12-01), Voss
patent: 4268848 (1981-05-01), Casey et al.
patent: 4470059 (1984-09-01), Nishizawa et al.
patent: 4574296 (1986-03-01), Suedka et al.

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