Semiconductor device with source/drain extension layer

Details Semiconductor device with source/drain extension layer Semiconductor device with source/drain extension layer

2006-10-10

2006-10-10

Williams, Alexander Oscar (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With provision for cooling the housing or its contents

C257S382000, C257S344000, C257S401000, C257S408000, C257S900000

Reexamination Certificate

active

07119435

ABSTRACT:
In a MOS transistor and a method of manufacturing the same, a gate structure including a gate insulating layer and a gate electrode is formed on a semiconductor substrate. A first insulating layer is formed to cover the gate structure. A second insulating layer is formed on the substrate that is spaced apart from the first insulating layer. A lightly doped source/drain region is formed in the surface portions of the substrate between the second insulating layer and the gate structure. A source/drain extension layer are formed on the lightly doped source/drain region. A heavily doped source/drain region is formed on the second insulating layer so as to connect with the source/drain extension layer. The short channel effect is suppressed and the source/drain junction capacitance is reduced.

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English Language Abstract of Japan Patent No.: JP8340113.
English Language Abstract of Japan Patent No.: JP8213616.

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