Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
2000-05-01
2002-06-25
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S019000, C257S192000, C257S195000, C257S196000
Reexamination Certificate
active
06410946
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, such as discrete devices or integrated circuit devices, and to a manufacturing method therefor.
2. Description of the Related Art
Recently, terminals used in mobile communication system, such as a mobile phone, have been actively developed so as to be compact and to have a low power consumption. Accordingly, semiconductor devices, such as transistors, composing the terminals, have also been required to have the same features as mentioned above. For example, a power amplifier for digital cellular use, which is considered to be the most important apparatus for current mobile communication, is required to be operated by a single positive power supply, and to have high efficiency at a low voltage.
Currently, one of the devices used in practice for a power amplifier is a heterojunction field-effect transistor (hereinafter referred to as HFET). A schematic structure of a conventional HFET, which performs current modulation by using a heterojunction thereof, is shown in FIG.
6
.
This HFET has a laminated structure formed on a base body
11
composed of a semi-insulating gallium-arsenide (GaAs), in which a buffer layer
12
composed of GaAs, a second barrier layer
13
composed of aluminum-gallium-arsenide (AlGaAs), a channel layer
14
composed of indium-gallium-arsenide (InGaAs), and a first barrier layer
15
composed of AlGaAs are sequentially formed.
The barrier layer
13
is composed of two high resistance layers
13
b
with a carrier supply layer
13
a
therebetween, and the barrier layer
15
is composed of two high resistance layers
15
b
with a carrier supply layer
15
a
therebetween.
A gate electrode
20
is disposed on the first barrier layer
15
, and at two sides of the gate electrode
20
, a source electrode
18
and a drain electrode
19
are ohmically formed above the first barrier layer
15
via cap layers
16
, respectively.
According to the structure described above, current between the source electrode
18
and the drain electrode
19
is modulated by a voltage applied to the gate electrode
20
.
In general, as shown in
FIG. 6
, the HFET has a recess structure in which a thickness of the first barrier layer under the gate electrode
20
and in the vicinity thereof is designed to be thinner in many cases. Consequently, an area in the channel layer under the recess formed in the first barrier layer, in which carriers are depleted or a smaller number of carriers are present compared to the other part of the channel layer, is formed.
In the HFET having the structure thus described, by applying a positive voltage to the gate electrode, carriers are accumulated in the channel layer, and hence a channel is formed.
The HFET having the structure thus described has advantages, in theory, of superior linearities of a gate-source capacitance Cgs and a mutual conductance Gm versus a gate voltage Vg, over other devices, such as a junction field-effect transistor (hereinafter referred to as JFET) and a Schottky junction field-effect transistor (hereinafter referred to as MESFET). This is of great advantage in order to achieve high efficiency in power amplifiers.
In the HFET having the structure thus described, current flowing into the drain electrode
19
reaches the channel layer
14
after passing through the cap layer
16
disposed under the drain electrode
19
and the first barrier layer
15
, and then the current flows into the source electrode
18
after passing along the channel layer
14
to a point below the source electrode
18
and passing through the first barrier layer
15
and the cap layer
16
disposed under the source electrode
18
.
The heavily doped cap layers
16
disposed under the drain electrode
19
and the source electrode
18
, respectively, in general function to reduce a contact resistance between a metal electrode and the high resistance layer
15
b
of the first barrier layer
15
.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device having no cap layers described above and a manufacturing method therefor, in which an etching step of the cap layers for forming a gate electrode can be eliminated, that is, manufacturing steps can be reduced.
In one aspect of the present invention, a semiconductor device comprises a base body, a channel layer formed on the base body, a first carrier supply layer formed on the channel layer for supplying carriers into the channel layer, in which the first carrier supply layer has a wider band cap than that of the channel layer, a first semiconductor layer formed on the first carrier supply layer and in ohmic contact with a source electrode and a drain electrode, and a gate electrode formed on the first semiconductor layer, wherein at least one of the source electrode and the drain electrode is in direct contact with the first semiconductor layer, and a doped area doped with an impurity having an opposite conductivity to that of the carriers is formed in the first semiconductor layer under the gate electrode.
The semiconductor device described above may further comprise a second carrier supply layer between the base body and the channel layer for supplying carriers into the channel layer, in which the second carrier supply layer has a wider band cap than that of the channel layer.
The source electrode and the drain electrode may be formed by an alloying treatment, and alloyed layers of the source electrode and the drain electrode may extend to the vicinity of the channel layer by the alloying treatment.
A thickness of at least one of the source electrode and the drain electrode may not be less than a depth from the top surface of the layers formed on the base body to the upper surface of the channel layer, and may not be more than 3,000 Å.
The channel layer may comprise indium-gallium-arsenide, and the first carrier supply layer may comprise aluminum-gallium-arsenide.
A thickness of the first semiconductor layer on which the gate electrode is formed may be less than those of the first semiconductor layer on which the source electrode and the drain electrode are formed.
The semiconductor device may further comprise a second semiconductor layer composed of the same material as that of the first semiconductor layer and formed between the carrier supply layer and the channel layer.
The semiconductor device of the present invention may further comprise a third semiconductor layer composed of the same material as that of the first semiconductor layer and formed between the second carrier supply layer and the channel layer, and a fourth semiconductor layer composed of the same material as that of the first semiconductor layer and formed between the second carrier supply layer and the base body.
In another aspect of the present invention, a semiconductor device comprises a semi-insulating base body, a buffer layer formed on the base body and composed of the same material as that of the base body, a channel layer formed on the buffer layer, a first carrier supply layer formed on the channel layer for supplying carriers into the channel layer, in which the first carrier supply layer has a wider band cap than that of the channel layer, a first semiconductor layer formed on the first carrier supply layer and in ohmic contact with a source electrode and a drain electrode, and a gate electrode formed on the first semiconductor layer, wherein at least one of the source electrode and the drain electrode is in direct contact with the first semiconductor layer, and a doped area doped with an impurity having an opposite conductivity to that of the carrier is formed in the first semiconductor layer under the gate electrode.
The semiconductor device described above may further comprise a second carrier supply layer between the buffer layer and the channel layer for supplying carriers into the channel layer, in which the second carrier supply layer has a wider band cap than that of the channel layer.
The source electrode and the drain electrode may be formed by an alloying tre
Dickey Thomas L
Sonnenschein Nath & Rosenthal
Sony Corporation
Tran Minh Loan
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