Semiconductor device with SOI structure

Details Semiconductor device with SOI structure Semiconductor device with SOI structure

1998-05-04

2003-04-01

Fahmy, Jr., Wael (Department: 2814)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

On insulating substrate or layer

C438S318000, C438S353000, C438S354000, C438S357000

Reexamination Certificate

active

06541345

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a SOI type semiconductor device using a bonded and etch-backed SOI substrate produced by selective polishing using a stopper, and a process of fabricating the same. In particular, the present invention relates to a SOIMOSFET having a structure such as a back gate electrode formed in a SOI substrate, and a process of fabricating the same.
2. Description of the Related Art
It has been known that a SOI (Silicon On Insulator) structure makes easy perfect isolation of elements and suppresses occurrence of a soft error and latch up inherent to a CMOSTr (Complementary Metal Oxide Semiconductor Transistor), and it has been relatively early examined to realize a high speed and high reliability CMOSTr-LSI by means of a SOI structure including a Si active layer having a thickness of about 500 nm.
In recent years, it has become apparent that the performances of the SOI structure can be more improved, for example, in terms of suppression of a short channel effect and enhancement of a current driving ability of the MOSTr by thinning a surface Si layer of the SOI structure to about 100 nm and controlling an impurity concentration in a channel at a relatively low value, thereby substantially depleting the entire Si active layer.
As a method for forming such a SOI layer, there has been known two relatively high level processes: a SIMOX (Separation by IMplanted OXygen) process and a wafer bonding process.
Each of these two processes, however, has a merit and a demerit at the present time. For example, a SOI substrate prepared by the SIMOX process is excellent in uniformity of thickness of a SOI film; however, it is poor in flatness at an interface with a buried oxide film, to degrade a reliability of a transistor. Besides, a SOI substrate prepared by the wafer bonding process is excellent in characteristic at an interface with a buried oxide film; however, it is particularly poor in uniformity of a thickness of a thin Si film.
Here, there will be briefly described steps of fabricating a SOI substrate in accordance with the wafer bonding process.
A SOI substrate is fabricated, in accordance with the wafer bonding process, by planarization-polishing and surface-treating a surface of an A substrate to be bonded, bonding a B substrate to the A substrate and annealing the bonded substrates A and B, and grinding and polishing the A substrate (selectively polishing, in the case of using a stopper). In the case of polishing the A substrate using a stopper, a-stepped-portion (which becomes a stopper layer) must be previously formed on the A substrate (which becomes the final SOI layer) before planarization-polishing the surface of the A substrate to be bonded.
The bonded and etch-backed wafer thus prepared is effective not only to relatively freely set a thickness of a buried oxide film and the like, but also to prepare a LSI in a state in which elements, interconnections, and the like are previously buried on the back side of the B substrate before bonding of the A substrate to the B substrate and hence to prepare a LSI of a higher degree of integration.
For example, in fabrication of a MOSFET, by burying a gate electrode (this is often called a back gate electrode) in a SOI substrate, it is possible not only to suppress a short channel effect and control a threshold voltage (Vth) and swing of a voltage in a transistor but also to apply the MOSFET to a X-MOS (a MOSTr allowing to simultaneously operate a front gate and a back gate, which is also called a “Double Gate MOS”).
Incidentally, the related art process of fabricating a semiconductor device has the following problems. Now, there will be reviewed these problems along with description of the related art fabrication process.
FIG. 26A
is a sectional view showing a process of fabricating a semiconductor device.
First, as shown in
FIG. 26A
, a photoresist film (not shown) is provided on a silicon substrate (A substrate) in a region in which a SOI layer
50
is to be formed. It should be noted that the positional relationship in the vertical direction shown in
FIG. 26A
is reversed to that in this description. The A substrate is anisotropically etched by RIE (Reactive Ion Etching) using the photoresist film as a mask, to form a stepped portion for forming the SOI layer
50
on the A substrate. In addition, the process of forming such a stepped portion is called a trench process (by anisotropic etching using RIE).
A back gate oxide film
53
is formed on the A substrate, and a back gate electrode
55
is formed on the back gate oxide film
53
. On the back gate electrode
55
is deposited an interlayer insulating film (SOI
2
film)
57
on which a poly-Si film (not shown) is formed. Then, the poly-Si film is planarized by polishing, and a supporting substrate (B substrate)
60
is bonded with the planarized surface of the poly-Si film.
The A substrate is polished from the back surface side using the back gate oxide film
53
as a stopper (this is called selective polishing), to prepare a semiconductor substrate (SOI substrate) having the SOI layer
50
, in which the back gate electrode
55
is buried.
A sacrifice oxide film (not shown) is formed by sacrifice oxidation on the surface of the SOI layer
50
exposed by the above selective polishing. The sacrifice oxidation is performed to recover the surface state of the SOI layer
50
coarsened by selective polishing.
On both the sacrifice oxide film and the back gate oxide film
53
is provided a silicon nitride film (oxidation preventive film, not shown) positioned on the SOI active layer
50
.
Next, by selectively oxidizing the back gate electrode
55
using the silicon nitride film (oxidation preventive film) as a mask, a thick oxide film
71
is formed on the back gate electrode
55
. At this time, the back gate electrode
55
is oxidized through an oxide film grown from the back gate oxide film
53
by sacrifice oxidation. Then, both the silicon nitride film and the sacrifice oxide film are removed, to expose the surface of the SOI layer
50
.
A front gate oxide film
61
is formed on the surface of the SOI layer
50
, and a front gate electrode
75
is formed on both the front gate oxide film
61
and the thick oxide film
71
. The step is followed by formation of a LDD (Lightly Doped Drain) region, a LDD-spacer (SOI
2
), and a diffusion layer.
Then, an interlayer insulating film
81
is formed on both the thick oxide film
71
and the front gate electrode
75
. In both the interlayer dielectric film
81
and the thick oxide film
71
are formed contact holes in which tungsten (W) plugs
77
are buried. And, aluminum (Al) interconnections
79
are formed on both the W plugs
77
and the interlayer insulating film
81
. In this state, one Al interconnection
79
is connected to the front gate electrode
75
through one W plug
77
and the other Al interconnection
79
is connected to the back gate electrode
55
through the other W plug
77
.
The above-described fabrication process is characterized by forming the oxidation preventive mask on a portion of the SOI region and selectively oxidizing the back gate electrode
55
, thereby making it possible to suppress a parasitic capacitance from being increased in the field area at a portion in which the front gate
75
is superimposed on the back gate electrode
55
.
However, in the case where the back gate electrode
55
in the field area is entirely oxidized as described above, as shown in
FIG. 26A
, upon formation of the first contact, the connection hole in which the W plug
77
connected to the back gate electrode
55
is to be buried is required to be formed in such a manner as to be deeper in thickness corresponding to that of the thick oxide film
71
than the connection hole in which the W plug
77
connected to the front gate electrode
75
is to be buried. As a result, an aspect ratio of the contact hole reaching the back gate electrode
55
is increased, so that there may occur a void
77
a
in the W plug
77
. This causes a problem that a contact resi

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