Semiconductor device with shallow n-type region with arsenic or

Details Semiconductor device with shallow n-type region with arsenic or Semiconductor device with shallow n-type region with arsenic or

1988-05-17

1989-10-17

Wojciecnowicz, Edward J.

357 59, 357 63, 357 89, 357 90, H01L 2972

Patent

active

048750859

ABSTRACT:
A method of forming a shallow n-type region of a semiconductor device such as a bipolar transistor and a MOS FET, including the steps of: forming a first film containing arsenic or antimony on a silicon substrate; forming a second film containing phosphorus on the first film; and diffusing the arsenic or antimony and the phosphorus into the semiconductor substrate out of the first and second films by heat-treatment. The diffused impurities of the arsenic or antimony and the phosphorus form the n-type region and the arsenic or antimony defines the depth of the n-type region.

REFERENCES:
patent: 4379726 (1983-04-01), Kumamaru et al.
patent: 4419810 (1983-12-01), Riseman
patent: 4542580 (1985-09-01), Delivorias
patent: 4549199 (1985-10-01), Yamauchi et al.

Affiliated with

Also associated with

Rating

Semiconductor device with shallow n-type region with arsenic or does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device with shallow n-type region with arsenic or , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device with shallow n-type region with arsenic or will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1746467