Electricity: electrothermally or thermally actuated switches – Electrothermally actuated switches – Fusible element actuated
Reexamination Certificate
2000-06-07
2002-04-30
Picard, Leo P. (Department: 2835)
Electricity: electrothermally or thermally actuated switches
Electrothermally actuated switches
Fusible element actuated
C337S297000, C337S159000, C337S416000, C257S209000, C257S529000, C438S601000
Reexamination Certificate
active
06380838
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to a semiconductor device with repair fuses and redundant circuits and a method of trimming the semiconductor device using a laser beam, which make it possible to save defective semiconductor devices by activating redundant circuits with the use of repair fuses as necessary. The present invention is preferably applied to fabrication of large-capacity semiconductor memory devices equipped with redundant or reserve memory cells.
2. Description of the Related Art
In recent years, large-capacity semiconductor memory devices typically have redundant circuits with reserve memory cells. If some of the memory cells in a semiconductor memory device are found defective in a testing operation, the defective memory cells are identified and replaced with reserve memory cells in the redundant circuits as necessary. Thus, the defect of the semiconductor memory device is repaired; in other words, the semiconductor memory device including the defective memory cells can be saved.
To activate the reserve memory cells in the redundant circuits (i.e., to use the redundant memory cells), after the defective memory cells are identified, they need to be electrically disconnected from the memory cell array and furthermore, the redundant or reserve memory cells need to be electrically connected to the same array instead. Such switching or replacement of electrical connection as explained here is usually realized by mechanically and electrically disconnecting specific wiring lines by way of the repair fuses provided beforehand in the device as necessary.
In the step of repairing the defective memory cell array or saving the defective semiconductor memory device, “redundancy analysis” is carried out on the basis of test result about whether the individual bit lines and word lines have gotten a pass or fail, thereby identifying the repair fuses to be fused and disconnected. Then, a laser beam is irradiated to the repair fuses thus identified using a laser repair system to disconnect the desired fuses. This step is termed the “laser trimming” step.
A method of repairing defective memory cells in a semiconductor memory device using redundant memory cells is briefly explained below.
FIGS. 1 and 2
show a typical configuration of a semiconductor memory device with redundant memory cells and repair fuses.
As shown in
FIG. 2
, the semiconductor memory device is equipped with a memory cell array
410
including memory cells, a redundant memory cell row
425
that corresponds to a memory cell row of the array
410
, and a redundant memory cell column
426
that corresponds to a memory cell column of the array
410
. The redundant row and column
425
and
426
are included in a redundant circuit.
Actually, the array
410
includes a large number of memory cells. However, for the sake of simplification of description, the array
410
is illustrated and explained as a 4×4 array, in other words, the array
410
has only four rows and four columns. Also, the following explanation is referred to the redundant memory cell row
425
alone, because the same explanation is applicable to the redundant memory cell column
426
.
As shown in
FIGS. 1 and 2
, the first memory cell row
421
having the Y address of
0
in the array
410
is connected to the output terminal of an AND circuit
431
. The second memory cell row
422
having the Y address of
1
in the array
410
is connected to the output terminal of an AND circuit
432
. The third memory cell row
423
having the Y address of
2
in the array
410
is connected to the output terminal of an AND circuit
433
. The fourth memory cell row
424
having the Y address of
3
in the array
410
is connected to the output terminal of an AND circuit
434
.
The rows
421
,
422
,
423
, and,
424
are respectively selected and activated when the output signals B
1
, B
2
, B
3
, and B
4
of the AND circuits
431
.
432
,
433
, and
434
have a value of “0”, i.e., they are in the state of logic low (L). On the other hand, when the output signals B
1
, B
2
, B
3
, and B
4
of the AND circuits
431
,
432
,
433
, and
434
have a value of “1”, i.e., they are in the state of logic high (H), the rows
421
,
422
,
423
, and
424
are respectively disconnected from the array
410
, i.e., they are inactivated.
The redundant memory cell row
425
is connected to the output terminal of an AND circuit
443
. The row
425
is selected and electrically connected to the array
410
(i.e., activated) when the output signal B
5
of the circuit
443
has a value of “1”.
The AND circuit
431
receives three input signals, i.e., an inverted signal of the selection signal A
0
, an inverted signal of the selection signal A
1
, and an inverted signal of the output signal D
1
of a NOT circuit
445
. Similarly, the AND circuit
432
receives the selection signal A
0
, the inverted signal of the selection signal A
1
, and the inverted signal of the output signal D
1
. The AND circuit
433
receives the inverted signal of the selection signal A
0
, the selection signal A
1
, and the inverted signal of the output signal D
1
. The AND circuit
434
receives the selection signal A
0
, the selection signal A
1
, and the inverted signal of the output signal D
1
.
An input terminal of an Ex-OR (Exclusive Or) circuit
441
receives the selection signal A
0
and another input terminal thereof is connected to a terminal of a fuse
451
and a terminal of a resistor
461
. The other terminal of the fuse
451
is connected to a power supply line supplied with a power supply voltage V
cc
. The other terminal of the resistor
461
is connected to the ground.
An input terminal of an Ex-OR circuit
442
receives the selection signal A
1
and another input terminal thereof is connected to a terminal of a fuse
452
and a terminal of a resistor
462
. The other terminal of the fuse
452
is connected to the power supply line of V
cc
. The other terminal of the resistor
462
is connected to the ground.
An input terminal of a NOT circuit
444
is connected to a terminal of a fuse
453
and a terminal of a resistor
463
. The other terminal of the fuse
453
is connected to the power supply line of V
cc
. The other terminal of the resistor
463
is connected to the ground.
The AND circuit
443
receives the output signal C
1
of the EX-OR circuit
441
, and the output signal C
2
of the EX-OR circuit
442
, and the output signal D
2
of the NOT circuit
444
. The NOT circuit
445
receives the output signal B
5
of the NAD circuit
443
.
The semiconductor memory device shown in
FIGS. 1 and 2
operates in the following way.
As described above, when the output signal B
5
of the AND circuit
443
has a value of “1”, the redundant memory cell row
425
is selected and activated. In this case, the output signal D
1
of the NOT circuit
445
(i.e., the redundant signal) has a value of “0” and therefore, all the AND circuits
431
,
432
,
433
, and
434
receive the signal value of “1”. Thus, any one of the output signals B
1
, B
2
, B
3
, and B
4
can be set to have a value of “1” by changing the combination of the values “0” and “1” in the selection signals A
0
and A
1
. This means that any one of the memory cell rows
421
,
422
,
423
, and
424
can be set nonselective, in other words, any one of the rows
421
,
422
,
423
, and
424
can be electrically disconnected from the array
410
. At the same time as this disconnection, the redundant row
425
is selected and electrically connected to the array
410
instead.
On the other hand, when the output signal B
5
of the AND circuit
443
has a value of “0”, the redundant row
425
is not selected. In this case, the output signal D
1
of the NOT circuit
445
(i.e., the redundant signal) has a value of “1” and therefore, all the AND circuits
431
,
432
,
433
, and
434
receive the signal value of “0”. Thus, all the output signals B
1
, B
2
, B
3
, and B
4
have a value of “0”, which means that all the rows
421
,
422
,
McGinn & Gibb PLLC
NEC Corporation
Picard Leo P.
Vortman Anatoly
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