Semiconductor device with reduced power consumption and thin fil

Details Semiconductor device with reduced power consumption and thin fil Semiconductor device with reduced power consumption and thin fil

1996-07-03

1998-03-10

Nelms, David C.

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3652257, G11C 514

Patent

active

057269459

ABSTRACT:
An SRAM according to the present invention includes a voltage-down circuit and an internal circuit. The voltage-down circuit includes three resistors, two PMOS transistors and an NMOS transistor. One PMOS transistor directly applies an external power supply voltage to the internal circuit. The NMOS transistor applies a voltage obtained by reducing the external power supply voltage by a threshold voltage thereof to the internal circuit. The value of a predetermined voltage as a condition for switching such application of the voltage by the PMOS transistor and application of the voltage by the NMOS transistor is determined by the resistance ratio of the two resistors. Each of the three resistors is formed by a plurality of resistance elements of one kind. Thus, even if the process parameter varies, the ratio of the resistance values of the two resistors which determines the switching point can be kept constant, thereby preventing variation in switching point.

REFERENCES:
patent: 5258947 (1993-11-01), Sourgen
patent: 5293334 (1994-03-01), Shimizu
patent: 5297099 (1994-03-01), Bolan et al.

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