Semiconductor device with reduced packaging stress

Details Semiconductor device with reduced packaging stress Semiconductor device with reduced packaging stress

1990-04-04

1991-09-03

Carroll, J.

357 54, H01L 2328, H01L 2934

Patent

active

050459180

ABSTRACT:
A semiconductor device contains a stress-relief layer (46) having a glass transition temperature of 25.degree. C. or less. The layer generally lies above an electrical interconnection system (12) in the device but does not overlie bond pad areas. This substantially alleviates thermally induced stress that could otherwise damage electronic components in the device while simultaneously allowing the maximum stress on electrical conductors (32 and 34) that protrude from the external package coating (48) to occur at bonding areas which can tolerate the stress. The layer preferably is a silicone polymer consisting of exposed photosensitive material.

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