Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Reexamination Certificate
2001-02-08
2002-04-16
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Addressing
Including particular address buffer or latch circuit...
C365S189050, C365S210130, C365S208000, C365S207000, C365S190000, C365S233100, C365S191000, C365S193000, C365S230060, C365S230080, C327S055000, C327S053000, C327S056000, C327S052000
Reexamination Certificate
active
06373782
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an input buffer that receives a signal from outside to transmit the signal to an internal circuit.
2. Description of the Background Art
A semiconductor device includes an input buffer that receives a signal input from outside. A conventional input buffer is constructed with a differential amplification circuit of a current mirror load and an inverter.
FIG. 8
is a circuit diagram showing a construction of a conventional input buffer
200
.
Referring to
FIG. 8
, the input buffer
200
includes a differential amplification circuit
202
that is activated in accordance with a signal EN and compares a reference voltage VREF with an input signal IN, and an inverter
204
that receives and inverts an output of the differential amplification circuit
202
and outputs an output signal OUT.
The differential amplification circuit
202
includes an N-channel MOS transistor
206
whose gate receives the signal EN and whose source is connected to a ground node, and an N-channel MOS transistor
208
whose gate receives the reference voltage VREF and whose source is connected to the drain of the N-channel MOS transistor
206
.
The differential amplification circuit
202
further includes an N-channel MOS transistor
210
whose gate receives the input signal IN and whose source is connected to the drain of the N-channel MOS transistor
206
, and a P-channel MOS transistor
212
whose gate and drain are connected to the drain of the N-channel MOS transistor
208
and whose source is connected to a power supply voltage Vcc.
The differential amplification circuit
202
further includes a P-channel MOS transistor
214
whose gate is connected to the drain of the N-channel MOS transistor
208
and which is connected between the node to which the power supply voltage Vcc is given and the drain of the N-channel MOS transistor
210
, and a P-channel MOS transistor
216
whose gate receives the signal EN and which is connected between the power supply node and the drain of the N-channel MOS transistor
210
. An output signal A of the differential amplification circuit
202
is output from the drain of the N-channel MOS transistor
210
.
The inverter
204
includes a P-channel MOS transistor
218
and an N-channel MOS transistor
220
both of which receive a signal A at the gates thereof and which are connected in series between the power supply node and the ground node. An output signal OUT is output from the connection node of the P-channel MOS transistor
218
and the N-channel MOS transistor
220
.
When the signal EN is raised to a H-level, the N-channel MOS transistor
206
is brought into a conducted state while the P-channel MOS transistor
216
is brought into a non-conducted state. Then, the differential amplification circuit
202
is activated and, if the input signal IN is higher than the reference voltage VREF, the differential amplification circuit
202
outputs a L-level to the signal A, whereas if the input signal IN is lower than the reference voltage VREF, the differential amplification circuit
202
outputs a H-level as the signal A.
However, regarding the amplitude of the output signal of the differential amplification circuit, it is not always the case that the H-level is the power supply voltage Vcc and the L-level is the ground voltage. There are cases in which the H-level of the output signal is lower than the power supply voltage Vcc or the L-level is higher than the ground voltage.
FIG. 9
is a waveform diagram for explaining an error operation of the input buffer.
Referring to
FIGS. 8 and 9
, the input signal IN is repeatedly at a higher voltage or at a lower voltage than the reference voltage VREF and, in accordance therewith, the output signal A of the differential amplification circuit
202
alternately outputs the H-level and the L-level. However, since the L-level of the signal A is higher than a threshold voltage Vt of the inverter
204
, the signal A does not cross over the threshold voltage of the inverter. Then, the output signal OUT of the inverter is fixed at the L-level.
Such a phenomenon occurs, for example, when the reference voltage VREF is low and, in such a case, it is difficult to raise the output of the differential amplification circuit above the threshold voltage of the inverter, thereby causing an error operation in which the output of the inverter remains invariable.
The threshold voltage of the inverter may change depending on production variations and, if the threshold value of the inverter changes, there is a problem of decrease in the production yield.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device including an input buffer that does not easily raise an error operation even under threshold voltage variations of the inverter caused by production variations.
In summary, the present invention is directed to a semiconductor device including an input buffer circuit and an internal circuit.
The input buffer circuit receives a first input signal from outside. The input buffer circuit includes first and second differential amplification circuits and an output circuit. The first differential amplification circuit compares a voltage given by the input signal with a reference voltage and outputs complementary first and second output signals in which a high level of an output voltage is a power supply voltage and a low level is a first intermediate voltage between the power supply voltage and a ground voltage. The second differential amplification circuit compares the voltage given by the first input signal with the reference voltage and outputs complementary third and fourth output signals in which a low level of an output voltage is the ground voltage and a high level is a second intermediate voltage between the power supply voltage and the ground voltage. The output circuit outputs complementary fifth and sixth output signals in accordance with the first to fourth output signals.
The internal circuit operates in accordance with the fifth and sixth output signals.
Therefore, a principal advantage of the present invention lies in that the error operation in which the input signal is not transmitted to the inside can be prevented when the threshold voltage variations occur due to process variations.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5708688 (1998-01-01), Ting et al.
patent: 5729160 (1998-03-01), Allan
patent: 5982705 (1999-11-01), Tsukikawa
patent: 55-149510 (1980-11-01), None
patent: 9-74340 (1997-03-01), None
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Tran Andrew Q.
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