Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – With specified electrode means
Reexamination Certificate
1999-12-29
2004-01-20
Nadav, Ori (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
With specified electrode means
C257S587000
Reexamination Certificate
active
06680522
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly to a transistor such as a vertical bipolar transistor, a field effect transistor or the like and its manufacturing method in which variation of electrical characteristic can be remarkably suppressed.
BACKGROUND OF THE INVENTION
The inventor of the present invention have proposed a vertical bipolar transistor and its manufacturing method which vertical bipolar transistor has a high cut-off frequency and in which reliable interconnection between conductor films or regions can be attained, in Japanese Patent No.2,551,353.
FIG. 16
is a rough sectional view of a conventional vertical bipolar transistor similar to the vertical bipolar transistor disclosed in Japanese Patent No.2,551,353.
In
FIG. 16
, reference number
201
shows a p-type silicon substrate which has a surface of (
100
) plane and an electrical resistivity of 10 to 20 &Sgr;-cm. Two kinds of buried layers of a few micrometers in thickness are formed on the surface of the silicon substrate
1
. The two kinds of buried layers are an n+ type buried layer
202
a
and a channel stopper p+ type buried layer
202
b
, which exist separately from each other. A collector n− type epitaxial silicon layer
203
is formed on the surfaces of these buried layers and on the surface of an area of the silicon substrate
201
where these buried layers do not exist. A silicon oxide film
204
is selectively formed to the depth reaching the p+ type buried layer
202
b
, and the silicon oxide film
204
forms an element isolation film. An n+ type collector lead-out region
205
connected to the n+ type buried layer
202
a
is formed by doping impurities in high concentration into a part of the collector n− type epitaxial silicon layer
203
. The portions described so far are collectively called a silicon basic body
200
.
A silicon oxide film
206
is formed on the silicon basic body
200
, and a base electrode p+ type polysilicon film
207
is selectively formed on the silicon oxide film
206
. And the base electrode polysilicon film
207
is covered with a silicon nitride film
208
. An opening
301
is formed so as to penetrate the silicon nitride film
208
and the base electrode p+ type polysilicon film
207
, and an opening
302
is formed so as to penetrate the silicon oxide film
206
. A collector epitaxial silicon layer
203
is partially exposed by these openings. This first opening
301
formed in the polysilicon film
207
is projected horizontally over the opening
302
from the edge of the second opening
302
. That is to say, the width of the second opening
302
is larger than the width of the first opening
301
.
A p+ type single crystal silicon intrinsic base
211
is formed on the collector epitaxial silicon layer
203
which is exposed by the second opening
302
. A p+ type polysilicon film
212
is formed on the side surface and the exposed lower surface of the base electrode polysilicon film
207
. Thus, the p+ type polysilicon film
212
connects the base electrode polysilicon film
207
and the intrinsic base
211
to each other.
An n++ type single crystal silicon emitter region
215
is provided in the middle area on the p+ type single crystal silicon intrinsic base
211
. A silicon oxide film
213
is formed so as to over the side wall of the opening. In the collector epitaxial silicon layer
203
directly under the base region and between the intrinsic base
211
and the n+ type buried layer
202
a
, there is formed an n type silicon collector region
214
in which the concentration of impurities is higher than that of impurities in the original collector epitaxial silicon layer
203
. An emitter electrode n++ type polysilicon
216
is provided on the n++ type single crystal silicon emitter region
215
. These regions are all covered with a silicon oxide film
217
.
Moreover, contact holes
303
a
,
303
b
and
303
c
which penetrate the silicon oxide film
217
and, depending upon places, penetrates also the silicon nitride film
208
and the silicon oxide film
206
are formed. Also, a metal film of aluminum-based alloy and the like is formed so as to fill these contact holes
303
a
,
303
b
and
303
c
, and furthermore a patterning process is applied to this metal film to form an emitter electrode
218
a
, a base electrode
218
b
and a collector electrode
218
c
. These emitter electrode
218
a
, base electrode
218
b
and collector electrode
218
c
composed of aluminum-based alloy are respectively in contact with the emitter electrode polysilicon
216
, base electrode polysilicon film
207
and collector lead-out region
205
.
A vertical bipolar transistor of the above-mentioned configuration shown in
FIG. 16
has an adequate high-speed operation characteristic, but has a problem of large variation or dispersion in an operating current. Concretely speaking, it can be explained as follows. In a bipolar transistor circuit, a differential transistor pair is formed by short-circuiting with each other the emitters of adjacent transistors. It is assumed that voltages to be applied to the bases so that the collector currents of the respective transistors of the differential transistor pair become equal to each other are respectively VB
1
and VB
2
. If the absolute value of the difference between these voltages, namely, the absolute value of “VB
1
−VB
2
” is defined as &Dgr;VB, the smaller this &Dgr;VB is, the more stable the circuit operation becomes. The reason is that in case that some number of stages of differential transistor pairs are combined inside the circuit, necessary input potentials vary due to occurrence of changeover among the differential transistor pairs. A vertical type bipolar transistor of the above-mentioned configuration shown in
FIG. 16
has a large value of this &Dgr;VB.
On the other hand, in a vertical bipolar transistor disclosed in Japanese Patent No.2,551,353, such a problem does not occur. This is because, the side surface of a base electrode polysilicon film is completely covered with an insulating film such as a silicon nitride film. However, in a vertical bipolar transistor disclosed in Japanese Patent No.2,551,353, the film thickness W
H
of an intrinsic base single crystal film formed by a selective crystal growth method is thinner than the spacing W
I
between the upper surface of the collector epitaxial silicon layer and the lower surface of the base electrode polysilicon film (W
H
<W
I
). Therefore, if the film thickness of a polysilicon film which selectively crystal-grows on the lower surface of the base electrode polysilicon film becomes too thin, another problem may occur that the intrinsic base is not connected to the base electrode polysilicon film. Thus, in the vertical bipolar transistor disclosed in Japanese Patent No. 2,551,353, it is necessary to strictly control a manufacturing process to avoid occurrence of such problem, and it is difficult to easily improve manufacturing yield and manufacturing cost.
Also, in the vertical bipolar transistor disclosed in Japanese Patent No. 2,551,353, in order to surely contact the intrinsic base and the base electrode polysilicon film, it is possible to consider that the film thickness W
H
of an intrinsic base single crystal film formed by a selective crystal growth method can be made thicker than the spacing W
I
between the upper surface of the collector epitaxial silicon layer and the lower surface of the base electrode polysilicon film (W
H
>W
I
). However, in such case, it has been found that there is a possibility that the intrinsic base single crystal film directly contacts the silicon nitride film covering the side wall of the base electrode polysilicon film and, thereby, a leak current of the bipolar transistor increases. The reason for this is considered that when the intrinsic base single crystal film contacts the silicon nitride film; s
Choate Hall & Stewart
Nadav Ori
NEC Electronics Corporation
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