Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-11-26
2003-03-04
Chaudhuri, Olik (Department: 2814)
Static information storage and retrieval
Floating gate
Particular connection
C365S185260
Reexamination Certificate
active
06529406
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-292001, filed Sep. 25, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, for example, ASIC (Application Specific Integrated Circuits), particularly to a memory macro installed with a logic circuit or the like.
2. Description of the Related Art
Recently, the multilevel interconnection technique has progressed, and data lines such as global wirings having a wide bus width, which comprises as many as 128 lines or more, are wired in a memory cell array. Such global wirings are often formed on a thick upper wiring layer to prevent signal-delay. On the other hand, these global wirings are hardly laid out on the whole area of a memory cell array so as to cover it. These global wirings generally are laid out with power supply wirings and other passing wirings. These power supply wirings and other passing wirings are arranged between global wirings in parallel with the global wirings. A plurality of power supply wirings arranged on a memory cell array may be formed in a direction along the global wirings. Thereby the total amount of resistance of power supply wiring in the direction along the global wirings can be reduced. However, it is difficult to arrange power supply wirings in a direction orthogonal to the global wirings so as to cross the global wirings. Thus the number of global wirings is extremely limited and the length and arranged position thereof are also limited. For example, one power supply wiring is arranged on one end of the global wirings in the direction orthogonal to the global wirings. Thereby, the total amount of resistance of the power supply wirings arranged in the direction orthogonal to the global wirings increases. In such a conventional arrangement of power supply wirings, it is difficult to supply a sufficient voltage to the whole area of the memory cell array.
Also, in the case of the conventional layout, a wirable region to arrange passing wirings can be formed in only one direction parallel with the global wirings. Such a wirable region laid out in only one direction has little utility for users, and it is hardly utilized. To solve the problem, a wiring layer is formed on an upper layer in a direction orthogonal to the wirable region. However, this creates a problem of increasing the cost of production.
Recently, a memory macro applied for ASIC, for example, a DRAM (Dynamic RAM) macro has been developed energetically. In a DRAM macro, easing the limitation of positions of power supply pins arranged in a macro and limitation of wirable regions for users passing through an upper layer of a macro is particularly required. That is, the area of the DRAM macro occupies several 10% of the total chip. Therefore the position of the DRAM macro in chip has a big influence on the floor plan of chip. As stated previously, for example, in a DRAM macro whose power supply wirings have a low resistance direction and a high resistance direction, a plurality of power supply pins must be arranged on a certain side of a macro. Because of this limitation, it is required that a DRAM macro be arranged in the vicinity of a power supply pad arranged on a peripheral portion of the chip. Further, when the direction of a wirable region for users passing through onto the DRAM macro is limited, DRAM macros are arranged on four corners of a chip to satisfy the limitation.
Also, a DRAM macro is required to have high operating frequency, wide bit width of data lines and the like. When the operating frequency is increased, current consumption increases. It is required that more power supply wirings are installed to make up for the increased current consumption. However, power supply wirings arranged merely between data lines is hardly adequate, thus it is required that power supply wirings are additionally arranged particularly in a direction orthogonal to data lines.
On the other hand, hierarchising data lines is effective in enlarging the bit width of the data lines. It is required that a wiring layer is added in order to realize hierarchising of data lines. However, data wirings added, for enlarging the bit width are required to be arranged in a direction parallel with existing data lines. In such a structure, power supply wirings are also arranged in parallel with existing power supply wirings. Therefore, it is difficult to reinforce power supply wirings arranged in a direction orthogonal to data lines. Further, a wirable region for users cannot be provided in the direction orthogonal to data lines. That is, it is required that at least two wiring layers are added in order to reinforce power supply wirings, add the width of data lines and provide a wirable region for users. However, in this case, there arises a problem of increasing the manufacturing steps and cost. Under circumstances, there has been demand of semiconductor device which can increase the number of power supply wirings, secure effective wirable regions for users and prevent increasing costs.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the invention, there is provided a semiconductor device comprising: a plurality of basic unit blocks, each basic unit blocks including a memory cell array having a plurality of memory cells arranged in a matrix, a first selecting line selecting one memory cell from the memory cells; a first data line arranged so as to orthogonalize with the first selecting line, the first data line transmitting data from the selected memory cell; and a sense amplifier connected to the first data lines, a plurality of second data lines formed in an upper layer of other basic unit blocks of a plurality of the basic unit blocks except a basic unit block positioned on one end, the plurality of second data lines being formed in the same direction of the first data line and being connected to the first data line; a first wiring arranged in an upper layer of the plurality of basic unit blocks, the first wirings running parallel with the second data line; and a second wiring arranged in an upper layer of the basic unit block positioned on the one end, the second wiring being arranged in a direction orthogonal to the first wiring.
REFERENCES:
patent: 5153685 (1992-10-01), Murata et al.
patent: 5969420 (1999-10-01), Kuge et al.
patent: 406209093 (1994-07-01), None
Yuji Yokoyama, et al., “A 1.8-V Embedded 18-Mb DRAM MACRO with A 9-ns RAS Access Time and Memory-Cell Area Efficiency of 33%”, IEEE Journal of Solid-State Circuits, vol. 36, No. 3, Mar. 2001, pp. 503-509.
Chaudhuri Olik
Farahani Dana
Kabushiki Kaisha Toshiba
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