Semiconductor device with polycrystalline silicon active region

Details Semiconductor device with polycrystalline silicon active region Semiconductor device with polycrystalline silicon active region

1991-01-22

1993-09-07

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 29, 437 41, 437 46, 437 34, H01L 21265

Patent

active

052428443

ABSTRACT:
A polycrystalline silicon layer is used to allow simultaneous fabrication of both N- and P-type MOSFET's on a common channel layer during integrated circuit fabrication. The polysilicon layer is between 20.ANG. and 750.ANG. thick, and preferably between 200.ANG. and 500.ANG. thick. These dimensions afford the polysilicon layer the high effective mobility, low threshold voltage and low leakage current characteristics, especially if the vapor-deposited polysilicon layer is annealed and/or ion implanted with Si.sup.+ or Ge.sup.+ after deposition. Application of the polysilicon layer over adjoining insulating and P-type semiconducting areas allows the single polysilicon layer to serve as active terminals and channels of both conductivity types of MOS transistors without intervening insulating or semiconducting layers. Deposition of the polysilicon layer in direct contact with a single-crystal substrate enhances the beneficial electrical properties of the polysilicon layer, especially if the polysilicon layer is annealed following deposition.

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