Semiconductor device with parallel multiplier using at least thr

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357 75, 364786, 364768, H01L 2348

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active

049790188

ABSTRACT:
In a semiconductor device of the present invention, partial products of a multiplicand and a specific bit of a multiplier are formed by a plurality of partial product producing circuits. The results of multiplication obtained from the partial product producing circuits are output to one of full adders serving as first partial sum producing circuits through a first connection wire formed of a first metal wiring layer and a second metal wiring layer formed above the first layer. In the first full adders, specific bits of the partial product producing circuits are grouped for addition. The result of this addition is output to a second full adder through a second connection wire formed of a third metal wiring layer formed above the second layer. In the second full adder, the results of addition obtained from the first full adders are added together, and then the result obtained from the second full adder is output to other full adders and a final full adder to obtain the product of the multiplicand and the multiplier.

REFERENCES:
patent: 4556948 (1985-12-01), Mercy
patent: 4605470 (1986-08-01), Gwozdz et al.

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