Semiconductor device with offset stacked integrated circuits

Details Semiconductor device with offset stacked integrated circuits Semiconductor device with offset stacked integrated circuits

2011-08-09

2011-08-09

Pham, Thanh V (Department: 2894)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S690000, C257S698000, C257S723000, C257S724000, C257SE25006, C257SE25013, C257SE25027, C438S074000, C438S109000

Reexamination Certificate

active

07994623

ABSTRACT:
A semiconductor device where multiple chips of identical design can be stacked, and the spacer and interposer eliminated, to improve three-dimensional coupling information transmission capability. A first semiconductor circuit including a three-dimensional coupling circuit (three-dimensional coupling transmission terminal group and three-dimensional coupling receiver terminal group); and a second semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode (power supply via hole and ground via hole); and a third semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode are stacked on the package substrate.

REFERENCES:
patent: 5629838 (1997-05-01), Knight et al.
patent: 2007/0274198 (2007-11-01), Kuroda et al.
patent: 2004-253816 (2004-09-01), None
patent: 2006-066454 (2006-03-01), None

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