Active solid-state devices (e.g. – transistors – solid-state diode – With metal contact alloyed to elemental semiconductor type... – In pn junction tunnel diode
Reexamination Certificate
2001-03-06
2004-02-10
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
With metal contact alloyed to elemental semiconductor type...
In pn junction tunnel diode
C257S104000, C257S105000, C257S106000
Reexamination Certificate
active
06690030
ABSTRACT:
CROSS-REFERENCE TO A RELATED APPLICATION
This application is related to Japanese Patent Application No. P2000-060185, filed on Mar. 6, 2000, the entire contents of which are incorporated.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly to functional devices utilizing negative differential resistance characteristics and also memory devices using load characteristics in addition thereto. The present invention also relates to a method of making the above-noted devices.
2. Discussion of the Background
To achieve higher performance and enhanced functionality of a silicon large-scale integration (LSI) circuit, static random access memory (SRAM) devices having an array of data storage cells with bistable characteristics have been proposed as memories suitable to achieve higher integration densities. Typically, the SRAM devices employ as their memory cells negative differential resistance such as Esaki diodes.
For example,
FIG. 33
depicts an equivalent circuit configuration of one typical SRAM cell. This cell employs a negative differential resistance
100
and a load
101
operatively associated therewith.
In the SRAM cell shown in
FIG. 33
, a series combination of the load
101
and the negative differential resistance
100
is connected between a high-voltage power supply Vdd and a low-voltage power supply Vss. The load
101
and the negative differential resistance
100
are serially connected together at a circuit node (data storage node). A metal-oxide-semiconductor (MOS) transistor is inserted between the storage node and a corresponding bit line BL. The MOS transistor is used as a data transfer, conduction of which is controlled by a voltage applied to a corresponding word line WL coupled to an insulated gate of the MOS transistor.
An operation of the SRAM using the load
101
and the negative differential resistance
100
will now be explained with reference to FIG.
34
. In more detail,
FIG. 34
graphically shows voltage-versus-current characteristics at the storage node of a cell using Esaki diodes as the negative differential resistance
100
and the load
101
, which are serially connected together in the forward-biased direction.
As shown in
FIG. 34
, one Esaki diode used as the load
101
exhibits a voltage-current curve D1. The remaining Esaki diode used as the negative differential resistance
100
shows a voltage-current curve D2. The curves D1, D2 have two stable points P0, P1. Information is stored so the stable points P0, P1 correspond to binary bit data. The states of these stable points P0, P1 will be read by the data-transfer MOS transistor.
Whereas traditional SRAM cells are designed so each cell requires four or six separate MOS transistors, the SRAM cell of
FIG. 33
using the negative differential resistance
100
and the load
101
requires a decreased number of elements (i.e., a single transfer MOS transistor in addition to the load
101
and the negative differential resistance
100
). This simple SRAM cell configuration makes it possible to reduce or “shrink” the memory cell occupation area on a chip (as taught from U.S. Pat. No. 4,573,143).
The SRAM with memory cells each using the load and negative differential resistance offers a demonstrable advantage over background SRAMs, because of the ability to attain higher on-chip integration. This can be said because the former is designable to employ highly miniaturized or more “compact” cells than ever before, as discussed previously.
Unfortunately, this advantage does not come without accompanying the following disadvantages. In more detail, it is difficult for the SRAM having the above-noted cell structure to satisfy the following conflicting requirements: low power consumption and high-speed operation performance. This “trade-off” problem occurs due to the necessity for reducing currents at the stable points to less than the order of magnitude of pico-amperes when attempting to lower electrical power consumed in wait modes, while on the contrary associating the need to increase such currents up to the order of magnitude of micro-amperes or more to achieve rapid charge-up/discharging of bit line capacitors when attempts are made to read storage information at high speeds.
Under the conflicting requirements, these current values exhibit an increased difference therebetween in excess of 6 orders of magnitude or greater. Simply controlling the high-voltage power supply cannot lead to successful achievement of both the power consumption reduction and the high-speed operability at the same time.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to solve the above-noted and other problems.
Another object of the present invention is to provide a novel semiconductor device, which employs a negative differential resistance and a load and which is capable of achieving both a low power consumption and a high-speed operability while at the same time offering increased on-chip integration densities.
To achieve these and other objects, the present invention provides in a first example a semiconductor device including a semiconductor substrate, a gate insulation film formed on the semiconductor substrate, a first conductive layer formed on the gate insulation film, a second conductive layer formed over the first conductive layer, and a channel region formed under the gate insulation film. Also included are spaced apart source and drain regions formed in the semiconductor substrate with the channel region placed therebetween, a load located between the first conductive layer and the second conductive layer, and a negative differential resistance located between the first conductive layer and the source region.
The present invention also provides in a second example a semiconductor device including a second conductive layer formed over the first conductive layer, and in which the negative differential resistance is located between the first conductive layer and the second conductive layer. Further, the load is located between the first conductive layer and the source region.
In yet another example, the present invention provides a semiconductor device including second and third conductive layers formed over the first conductive layer, and in which the negative differential resistance is located between the first conductive layer and the second conductive layer. Further, the load is located between the first conductive layer and the third conductive layer.
REFERENCES:
patent: 4132904 (1979-01-01), Harari
patent: 4573143 (1986-02-01), Matsukawa
patent: 5032891 (1991-07-01), Takagi et al.
patent: 5349206 (1994-09-01), Kimura
patent: 5936265 (1999-08-01), Koga
patent: 6133093 (2000-10-01), Prinz et al.
Koga Junji
Ohba Ryuji
Toriumi Akira
Uchida Ken
Flynn Nathan J.
Wilson Scott R
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