Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2002-03-01
2004-04-06
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S618000, C257S770000, C257S366000
Reexamination Certificate
active
06717271
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based on Japanese patent applications No.2001-236301, filed on Aug. 3, 2001, and No. 2002-019361, filed on Jan. 29, 2002, the whole contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having a so-called mushroom electrode and its manufacture method.
B) Description of the Related Art
The operation speed of a field effect transistor depends upon the gate length along the current path direction. In order to speed up a field effect transistor, it is desired to shorten the gate length. If the resistance of the gate electrode increases, a high speed operation of the transistor is restrained. In order to lower the gate electrode resistance, it is desired to set the cross sectional area of the gate electrode to a predetermined value or larger.
These requirements can be met by a mushroom type gate electrode which has a limited size of a lower part and a magnified size of the upper part. A generally upright lower part of the mushroom electrode is called a stem and the upper part with the magnified cross sectional area is called a head. A mushroom gate electrode is formed by vapor-depositing a gate electrode layer on a photoresist layer having a lower opening with vertical side walls and an upper expanded opening, and lifting off the resist layer.
As the aspect ratio of a vertical opening to be formed in a resist layer becomes large, it becomes difficult to uniformly bury the lower vertical opening with a gate electrode layer. In order to mitigate this difficulty, it has been proposed to form an upwardly broadening lower opening of a forward taper shape in a resist layer, and vacuum-deposit an upwardly broadening gate electrode stem of a forward taper shape without forming any void.
In forming an upward broadening gate electrode stem of a forward taper shape, it is important to reliably control a gate length and a contact cross section between semiconductor and the gate electrode in order to improve the performance and reliability of the device. A conventional tapering method is, however, insufficient in that a uniform opening shape and a gate electrode cross-sectional shape at the contact area between semiconductor and the gate electrode cannot be formed reliably.
If a field effect transistor to be formed has a gate length longer than 0.15 &mgr;m, a mushroom gate electrode can be formed without any problem by forming a lower opening with generally vertical side walls in a photoresist layer. If a device having a gate length equal to or shorter than 0.15 &mgr;m is formed by a conventional method, a manufacture yield of gate electrodes lowers.
It is desired to form an upwardly broadening resist opening of a forward taper shape for forming the stem of the gate electrode.
In forming an upwardly broadening gate electrode of a forward taper shape by a conventional method, a gate electrode stem opening is formed in a resist layer and is forwardly tapered by utilizing glass transition. This conventional method has, however, poor controllability so that a uniform gate length is difficult to be set. Because of poor controllability, the cross section at the contact between semiconductor and the gate electrode is difficult to be controlled and an operation speed and reliability of devices cannot be improved.
A fine gate opening for a conventional mushroom gate having a high aspect ratio is upwardly broadened by utilizing resist glass transition. This method has, however, poor controllability and is difficult to obtain a uniform opening length, i.e., gate length. Because of poor controllability, it is difficult to control the cross section of the contact area between semiconductor and the gate electrode and improve the operation speed and reliability of devices.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device having a fine gate capable of being manufactured with a high yield.
It is another object of the invention to provide a method of highly reliably manufacturing a semiconductor device with a fine gate.
It is another object of the invention to provide a semiconductor device having electrodes with various characteristics, the electrodes being made of the same layer.
It is another object of the invention to provide a semiconductor device manufacture method capable of forming electrodes with various characteristics by the same process.
According to one aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate having a pair of current input/output regions via which current flows; a first insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the first insulating film near at a position of at least one of opposite ends of the stem along the current direction.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: (a) preparing a semiconductor substrate having a pair of current input/output regions; (b) forming an insulating layer on the semiconductor substrate; (c) forming a resist laminate on the insulating layer; (d) forming an upper opening through an upper region of the resist laminate, the upper opening having a laterally broadened middle space; (e) forming a lower opening through a lower region of the resist laminate, the lower opening communicating the upper opening, having a limited size along a current direction, and having generally vertical side walls; (f) etching the insulating film exposed in the lower opening; (g) performing a heat treatment of the resist laminate to deform the side walls of the lower opening so that at least one of opposite ends of the lower opening is retracted or retarded from a corresponding end of the insulating layer and that the lower opening has a forward taper shape upwardly and monotonically increasing a size of the lower opening along the current direction; and (h) filling a gate electrode stem in the lower opening and forming a head in the upper opening, the head having an expanded size along the current direction.
According to another aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate having a plurality of transistor regions; and a plurality of mushroom gate electrode structures formed on the semiconductor substrate in the plurality of transistor regions, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction, and the head having a size expanded stepwise along the current direction, wherein at least some of the mushroom gate electrode structures have each a taper shape upwardly and monotonically increasing a size along the current direction, and the taper shapes have different angles in different transistor regions.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of (a) preparing a semiconductor substrate having a plurality of element regions; (b) forming a resist laminate on the semiconductor substrate; (c) applying an energy beam to an upper region of said resist laminate for defining an upper opening in each of said plurality of element regions, and applying an energy beam
Ikechi Naoya
Makiyama Kozo
Tan Takahiro
Flynn Nathan J.
Fujitsu Limited
Greene Pershelle
Westerman Hattori Daniels & Adrian LLP
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