Semiconductor device with multi-level wiring in a gate array

Details Semiconductor device with multi-level wiring in a gate array Semiconductor device with multi-level wiring in a gate array

1984-04-11

1990-01-09

James, Andrew J.

357 45, H01L 2710, H01L 2952

Patent

active

048931705

ABSTRACT:
A semiconductor device is designed and layed out to have a multiple-layer wiring structure and a logic gate cell structure. The multiple-layer wiring structure is constituted by wiring layers each being a vertical wiring layer for producing vertical wirings or a horizontal wiring layer for producing horizontal wirings, and either of the vertical or horizontal wiring layer is provided in plurality. One of the layers of the plurality of wiring layers is that for producing wirings which constitute input terminals of logic gates, and another layer of the plurality of wiring layers is that for producing wirings which constitute output terminals of logic gates. Wiring is carried out along each wiring grid which is provided for each of the plurality of wiring layers so that lines of different grids are alternately arranged.

REFERENCES:
patent: 4412237 (1983-10-01), Hatsumura et al.

Affiliated with

Also associated with

Rating

Semiconductor device with multi-level wiring in a gate array does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device with multi-level wiring in a gate array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device with multi-level wiring in a gate array will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-148487