Semiconductor device with metal-oxide conductors

Details Semiconductor device with metal-oxide conductors Semiconductor device with metal-oxide conductors

1999-05-14

2002-05-28

Abraham, Fetsum (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S072000, C257S347000, C257S771000

Reexamination Certificate

active

06396147

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a structure production process of a semiconductor device such as a insulated gate type transistor having wiring formed with an aluminum material. The semiconductor device of the invention includes not only a device such as a thin film transistor and a MOS transistor but also an electronic apparatus, such as a display apparatus and an image sensor, having a semiconductor circuit constituted with such an insulated gate type transistor.
BACKGROUND OF THE INVENTION
In recent years, an active matrix type liquid crystal display having a pixel area and a driving circuit constituted with a thin film transistor (hereinafter abbreviated as TFT) formed on a substrate having an insulating property receives attention. A liquid crystal display includes one having a size of from 0.5 to 2 inches for a projection display and one having a size of from 10 to 20 inches for a portable computer, and is used as a display device of a small size to a middle size.
In recent years, a liquid crystal display having a large area is being demanded. In a liquid crystal display of a large area, the area of a pixel matrix area as an image display part becomes large, and thus source wiring and gate wiring arranged in a matrix form become long, which results in increase in wiring resistance. The wiring should be thin due to a demand of minuteness, and the increase in wiring resistance is tangible. Furthermore, since the source wiring and the gate wiring are connected to a TFT for each pixel, and there arises a problem of increase in parasitic capacity. In a liquid crystal display, since gate wiring and a gate electrode are unitedly formed, delay of a gate signal becomes tangible along with increase in area of the panel.
Accordingly, a material mainly comprising aluminum having a relatively low resistance is used as the gate wiring. By forming the gate wiring and the gate electrode with a material mainly comprising aluminum, the gate delay time can be lowered, and the device can be operated at a high speed.
An attempt of decreasing an off current has been conventionally made by making a thin film transistor having an offset structure or an LDD (light doped drain) structure. In Japanese Patent No. 2,759,415, the inventors propose a thin film transistor of an LDD structure. The Japanese Patent No. 2,759,415 corresponds to a U.S. Pat. No. 5,648,277. The Japanese Patent No. 2,759,415 and the U.S. Pat. No. 5,648,277 disclose a process for forming an LDD structure in a semiconductor layer in a self alignment manner by using aluminum as a gate electrode material and subjecting the gate electrode to anodic oxidation. The process will be described with reference to
FIGS. 38A
to
38
E. An entire disclosure of the Japanese Patent No. 2,759,415 and the U.S. Pat. No. 5,648,277 is incorporated herein by reference.
An underlayer film
1011
, such as a silicon oxide film, is formed on a glass substrate
1010
. An active layer
1013
comprising a polycrystalline silicon film is formed on the underlayer film
1011
,and a gate insulating film
1014
is formed on the active layer
1013
. An aluminum film is formed and patterned by using a photoresist mask
1016
to form a gate electrode
1015
comprising aluminum. (
FIG. 38A
)
The pattern is subjected to anodic oxidation in an electrolytic solution by using the gate electrode
1015
as an anode to form a porous alumina film
1017
. In this stage, since the surface of the gate electrode
1015
is covered with the mask
1016
, the alumina film
1017
is formed only on the side surface of the gate electrode
1015
. (
FIG. 38C
)
After removing the photoresist mask
1016
, the gate electrode
1015
is again subjected to anodic oxidation to form a non-porous alumina film
1018
. (
FIG. 38B
)
The gate insulating film
1014
is patterned by using the alumina films
1017
and
1018
as a mask. (
FIG. 38D
) The porous alumina film
1017
is then removed.
After obtaining this state, the active layer
1013
is doped with an impurity endowing an n-type or p-type conductivity by a plasma doping method. The doping is conducted as divided into two stages. The first stage is conducted at such low acceleration that the gate insulting film
1014
functions as a mask with a large dose amount. The second stage is conducted at such high acceleration that the impurity passes through the gate insulating film
1014
with a small dose amount. As a result, a channel forming region
80
, a source region
81
, a drain region
82
and low concentration impurity regions
93
and
84
are formed in the active layer
1013
in a self alignment manner. The low concentration impurity region
84
in the side of the drain region
82
is the LDD region.
However, in order to conduct the anodic oxidation treatment, all the electrodes and wiring to be subjected to anodic oxidation should be connected to voltage supplying wiring for anodic oxidation. For example, in the case where the technique disclosed in the literature described above is applied to an active matrix type liquid crystal panel, the gate electrodes and wiring of the thin film transistor constituting the active matrix area and the driver circuit should be connected to voltage supplying wiring. In order to make such a connection, voltage supplying wiring is formed on the substrate, which results in increase of the area of the substrate.
Each gate electrode and gate wiring forms a short circuit with the voltage supplying wiring, and after the anodic oxidation treatment, unnecessary connected parts to the supplying wiring are removed by etching to separate the respective gate wiring and gate electrodes. Therefore, the circuit should be designed with consideration of a process margin of the etching process.
Accordingly, in order to produce a transistor by using the anodic oxidation treatment, additional area for forming the voltage applying wiring and the etching margin are required, which become a bar to the production of a highly integrated circuit and the decrease in area of the substrate.
Furthermore, since aluminum is used as the material of the gate electrode
1015
in the literature described above, the alumina film
1018
is made of alumina. Therefore, the alumina film should be etched in order to connect the gate wiring and the leading wiring. The inventors have used buffered hydrofluoric acid (a mixed solution of ammonium fluoride and hydrofluoric acid) is used as an etchant on the etching.
However, the buffered hydrofluoric acid is low in selectivity between alumina (representative example thereof is Al
2
O
3
) and aluminum, and thus there is a problem in that it etches not only the alumina film but also the gate wiring thereunder. The problem will be described with reference to FIG.
39
.
In
FIG. 39
, numeral
1031
denotes a substrate having an insulating surface,
1032
denotes an insulating film comprising silicon oxide (which functions as a gate insulating film on the active layer),
1033
denotes gate wiring comprising aluminum,
1034
denotes an alumina (anodic oxidized) film obtained by subjecting the gate wiring
1033
to anodic oxidation.
When a part of an upper surface of the alumina film
1034
is etched with the buffered hydrofluoric acid, the gate wiring
1033
is firstly exposed. In general, since the etching is conducted with a certain distribution within the surface of the substrate, it is necessary to completely remove the alumina film
1034
by over-etching.
At this time, when the over-etching is excessively conducted, the gate wiring
1033
is etched by the buffered hydrofluoric acid. There is a possibility that an etching hole
1035
reaches the insulating film
1032
through the gate wiring
1033
.
When such a situation is developed, the gate wiring
1033
is connected to the leading line (not shown in the figure) only on a cross section
1036
(expressed by thick lines) of the gate wiring
1033
. Because the diameter of the general contact hole is several micrometers, whereas the film thickness of the gate wiring is several hundreds nm, the area on which the gate wiring a

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