Semiconductor device with low parasitic capacitance

Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Having diverse electrical device

Reexamination Certificate

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Details

C438S026000, C438S516000, C438S520000, C438S537000

Reexamination Certificate

active

06287881

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the field of optoelectronics, and more particularly to light emitting diodes, such as VCSELs (Vertical Cavity Surface Emitting Lasers).
BACKGROUND OF THE INVENTION
VCSELs, or Vertical Cavity Surface-Emitting Lasers, are semiconductor mirolaser diodes that emit light vertically from the surface of a fabricated wafer. VCSELs have many advantages including photolithographically defined geometries, circular output beams, high fiber optic coupling efficiencies, extremely low power consumption, and ultra-high modulation rates for advanced information processing. VCSELs are finding increasing application in the telecommunications industry due to their high performance with narrow linewidth.
In the design of an emitting device, it is common practice to provide a monitoring device, such as a photodiode. The monitor is placed under the emitting device or on the same substrate as the emitting device adjacent to it. This is used to monitor light output for control purposes. The output of the monitoring device can be used control the drive conditions of the emitting device. This can be used to maintain the optical output of a VCSEL at a constant power level. In many cases, it is desirable to mount the emitting device on top of a monitor. In many cases, it is desirable to mount the monitoring device on top of the VCSEL. The problem with this arrangement is that it a parasitic capacitance occurs between the devices. Depending on the pin configuration, the capacitance may significantly deteriorate the high frequency properties of the emitting component. For example, the output of the VCSEL is lowered at higher speeds.
Due to this effect, the number of possible pin configurations is limited for high frequency applications, for example, gigabit data communication. An object of the invention is to alleviate this problem.
SUMMARY OF THE INVENTION
According to the present invention there is provided a method of fabricating a semiconductor device having at least one active component grown on a substrate, comprising the steps of providing a semiconductor substrate on which said active components are grown; and doping or implanting said semiconductor substrate to render it non conductive and thereby reduce parasitic capacitance between active components thereon or between it and a surface on which it is mounted.
The substrate is normally doped prior to growing the components. The substrate should be semi-isolating or have its backside made non-conductive by ion implantation, for example, with ions of hydrogen, oxygen, or helium. The non-conductivity can be obtained before growth of the emitting component(s), for example, by growth on a non-conductive sample, or after the growth of the emitting components, for example, by implantation or fusion to a non-conductive substrate.
The invention is specifically applicable to a VCSEL and monitoring device, such as a photodetector. The invention permits the fabrication of n-type VCSELs with maximum performance and different types of monitor or metal plated area with low parasitic capacitance.
The invention also provides a semiconductor device having active components grown on a substrate, comprising a plurality of active components; and a semiconductor substrate supporting said active components, said semiconductor substrate being doped or implanted to render it non conductive and thereby reduce parasitic capacitance between said active components thereon.


REFERENCES:
patent: 3748480 (1973-07-01), Coleman
patent: 3881113 (1975-04-01), Rideout et al.
patent: 4124860 (1978-11-01), Johnson
patent: 4136351 (1979-01-01), Sugawara et al.
patent: 4143385 (1979-03-01), Miyoshi et al.
patent: 4274104 (1981-06-01), Fang et al.
patent: 4275404 (1981-06-01), Cassiday et al.
patent: 5018004 (1991-05-01), Okinaga et al.
patent: 5346841 (1994-09-01), Yajima
patent: 0753912 (1997-07-01), None
patent: WO 93/07647 (1993-04-01), None

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