Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2002-01-28
2004-10-05
Nguyen, Cuong (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S306000
Reexamination Certificate
active
06800922
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention provides a capacitor for a ferroelectric memory and the like, and a process for manufacturing the same. More particularly, the present invention relates to a process for manufacturing a semiconductor device which has a capacitor comprising a lower electrode layer, a ferroelectric layer and an upper electric layer, which can suppress a peeling between the layers while maintaining electrical properties of the ferroelectric layer.
2. Prior Art
Ferroelectric memories in the semiconductor field have recently attracted attention. A ferroelectric memory is a next generation memory which is characterized by quick response, random access, multiple rewriting, low power consumption and the like. In the current ferroelectric memory, a transistor is formed, followed by formation of a capacitor comprising an electrode and a ferroelectric layer. These steps are usual processes as described in the Example of JP-A 11-214655. An embodiment of the prior art will be explained below using
FIGS. 5A-5G
.
First, on an underlying substrate
21
on which a transistor has been formed, an adhesion layer
22
is deposited to 50 nm by sputtering, for example, TiO
2
, TiN and the like. A lower electrode layer
23
is deposited thereon to 200 nm by sputtering, for example, Pt, Ir, IrO
3
and the like. In addition, for example, SBT, PZT and the like is deposited by a Sol-Gel method, MOD, LSMC, sputtering, CVD and the like to 200 nm to form a ferroelectric layer
24
thereon, and which is sintered in an O
2
atmosphere. Further, an upper electrode layer
25
is deposited thereon to 100 nm by sputtering, for example, Pt, Ir, IrO
3
and the like (FIG.
5
A).
After that, a 1.5-&mgr;m thick photoresist pattern
26
for processing the upper electrode is formed on the upper electrode layer
25
. The upper electrode
25
is then processed by dry etching (FIG.
5
B). Dry etching is performed mainly by sputter etching with Ar by highly dissociating a mixture gas of Cl
2
and Ar under a high vacuum at 3 mTorr or less, for example, on a high density plasma etching apparatus using an Inductive Coupling Plasma (ICP) and the like. Generally, since vapor pressures of Pt and Ir are very low due to their low reactivity, Pt and Ir dissociated by sputter etching re-adhere to a sidewall of the pattern even after etching. By adding Cl
2
, F
2
and the like to the etching gas, materials adhering on the sidewall are converted to chlorine or fluorine and the like so that they can be removed in the later step of washing.
Then, an etching deposit
27
adhering to the sidewall of the pattern is removed. Subsequently, a remaining resist pattern is removed by using a down flow O
2
ashing apparatus and the like (FIG.
5
C).
Subsequently, a 2.0-&mgr;m thick photoresist pattern
28
for processing a ferroelectric layer is formed on the processed upper electrode layer
25
and the ferroelectric layer
24
, and the ferroelectric layer
24
is processes by dry etching (FIG.
5
D). Since a ferroelectric layer has similar etching properties to those of Pt, Ir and the like, etching is performed under similar conditions and by a similar mechanism to those for etching the upper electrode layer.
After that, the etching depot-deposit
29
adhering to the pattern side wall is removed by washing. A remaining resist is then removed by down flow O
2
ashing and the like (FIG.
5
E).
Similarly, a 2.0-&mgr;m thick photoresist pattern
30
for processing a ferroelectric layer is formed on the processed upper electrode layer
25
, the processed ferroelectric layer
24
and the lower electrode layer
23
, and the lower electrode layer
23
is processed by dry etching (FIG.
5
F).
Since the lower electrode layer is made from a similar material to that for the upper electrode layer, etching is performed by using a similar condition and mechanism.
After that, the etching deposit
31
adhering to the pattern side wall is removed by washing. A remaining resist is then removed by down flow O
2
ashing and the like (FIG.
5
G).
When the capacitor shape is formed according to the above steps, the ferroelectric properties are deteriorated by dry etching and washing. Therefore, at the last step, after processing the capacitor, the ferroelectric layer is re-sintered by annealing at a temperature as high as or higher than the carcining (or sintering) temperature at which the ferroelectric layer is formed, to recover its electrical properties. By undergoing the above steps, the capacitor of the ferroelectric layer is formed.
However, this conventional process has a problem in that a layer-peeling phenomenon occurs between an electrode layer and a ferroelectric layer when a capacitor is formed.
FIG. 6
illustrates upper electrode layer
25
peeling from ferroelectric layer
24
.
The layer-peeling phenomenon occurs when a deposit is washed after etching each of the layers, and in a final annealing. Therefore, it can be considered that a lift-off phenomenon caused by penetration of a solution (for washing a deposit) into a gap between the electrode layer and the ferroelectric layer, and interlayer separation due to a difference in a layer shrinkage rate between the electrode layer and the ferroelectric layer in annealing directly result in the layer peeling.
From an examination of the conventional semiconductor devices, that peeling of the upper electrode layer tends not to occur as the surface morphology of the ferroelectric layer becomes worse. On the other hand, with better surface morphology of the ferroelectric layer (that is, the denser film density) better electric properties result. Therefore, it is currently difficult to improve electrical properties and to decrease film peeling simultaneously, resulting in a big problem.
It has been proposed to attempt prevent the peeling by putting a dielectric layer with a high adherability between the electrode layer and the ferroelectric layer. Yet such proposal has definite disadvantages such as deterioration in electrical properties of the ferroelectric layer, process complication and the like. Thus, an optimal method has not vet been established.
SUMMARY OF THE INVENTION
Thus, an object of the present invention is to suppress the peeling phenomenon in a semiconductor device comprising at least a ferroelectric layer and an upper electrode formed thereon while maintaining the electrical properties of the ferroelectric layer.
According to the present invention, peeling between a first layer and an upper layer formed on the first layer is prevented. Whereas heretofore peeling has been caused by penetration between the layers of a bath or a layer shrinkage in a step of heating, the surface of the first layer is uniquely formed to resist peeling. A since convex or concave region is formed on a surface of a first layer by etching, resulting in an interface between the layers configured to resist the peeling (referred to as an “anchor effect”).
REFERENCES:
patent: 5245505 (1993-09-01), Shiga et al.
patent: 5798903 (1998-08-01), Dhote et al.
patent: 6010969 (2000-01-01), Vaartstra
patent: 6472124 (2002-10-01), Chung
patent: 0933783 (1999-08-01), None
Nguyen Cuong
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
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