Semiconductor device with latency counter

Details Semiconductor device with latency counter Semiconductor device with latency counter

2008-07-01

2008-07-01

Lam, Tuan T (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Pulse counting or dividing chains

C377S122000, C377S124000

Reexamination Certificate

active

11543233

ABSTRACT:
A latency counter of a semiconductor device comprises a single cyclic signal generator and a command delay circuit. The single cyclic signal generator cyclically produces 0-th to n-th base signals based on an internal clock signal. The command delay circuit comprises 0-th to n-th latch elements and latches an internal command by means of a p-th latch element (p is an integer; 0≦p≦n) in response to a q-th base signal (q is an integer; 0≦q≦n) and to output the latched internal command corresponding to the latency timeout signal therefrom in response to a r-th base signal (r is an integer; 0≦r≦n), where r=q+s if q+s≦n, while r=q+s−(n+1) if q+s>n, s being a natural number equal to or less than n.

REFERENCES:
Song et al., “A 1.2Gb/s/pin Double Data Rate SDRAM with On-Die-Termination,” IEEE International Solid-State Circuits Conference 2003/Session 17/SRAM and DRAM/Paper 17.8, 2003.

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