Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2002-05-02
2004-04-27
Williams, Alexander Oscar (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S700000, C257S701000, C257S751000, C257S759000, C257S784000, C257S211000, C257S208000
Reexamination Certificate
active
06727590
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and particularly to a semiconductor device having a multilayer interconnection structure with aluminum (Al) interconnections in lower layers and copper (Cu) interconnections in upper layers.
2. Description of the Background Art
FIG. 26
is a cross-sectional view showing the structure of a conventional semiconductor device using aluminum interconnections. An element isolation insulating film
102
formed of a silicon oxide film (SiO
2
) is partially formed on a silicon (Si) substrate
101
. Semiconductor elements such as MOSFETs
106
are formed in an element formation region defined by the element isolation insulating film
102
. Each MOSFET
106
has a gate electrode
104
formed on an upper surface of the silicon substrate
101
with a gate insulating film
103
interposed therebetween, and a pair of source/drain regions
105
formed in the upper surface of the silicon substrate
101
with a channel formation region under the gate electrode
104
being interposed between the source/drain regions
105
. While
FIG. 26
shows gate electrodes
104
formed on the element isolation insulating film
102
, the gate electrodes
104
of MOSFETs which are present in the depths of, or on this side of the paper extend on the element isolation insulating film
102
.
An underlying insulating film
107
is formed all over the silicon substrate
101
to cover the MOSFETs
106
and the element isolation insulating film
102
. The underlying insulating film
107
is formed of a silicon oxide film or a silicon oxide film implanted with an impurity element such as phosphorus (P) or boron (B). Contact holes
108
are formed in the underlying insulating film
107
and connected to the MOSFETs
106
. First-layer interconnections
109
, made of tungsten (W), are formed partially on the underlying insulating film
107
. The first-layer interconnections
109
, which are local interconnections, are short in length. The first-layer interconnections
109
are connected to the MOSFETs
106
through the tungsten which fills the contact holes
108
.
A first interlayer insulating film
110
is formed on the underlying insulating film
107
to cover the first-layer interconnections
109
. The first interlayer insulating film
110
is formed of a silicon oxide film or the like. Via holes
111
are formed in the first interlayer insulating film
110
and connected to the first-layer interconnections
109
. The via holes
111
are filled with via plugs
112
made of tungsten or the like. Second-layer interconnections
113
, made of an aluminum alloy such as Al—Cu, Al—Si—Cu, Al—Cu—Ti, etc., are partially formed on the first interlayer insulating film
110
. The second-layer interconnections
113
, which are short-distance interconnections, are relatively short in length. The second-layer interconnections
113
are connected to the first-layer interconnections
109
through the via plugs
112
.
A second interlayer insulating film
114
is formed on the first interlayer insulating film
110
to cover the second-layer interconnections
113
. The second interlayer insulating film
114
is formed of a silicon oxide film or the like. Via holes
115
are formed in the second interlayer insulating film
114
and connected to the second-layer interconnections
113
. The via holes
115
are filled with via plugs
116
made of tungsten or the like. Third-layer interconnections
117
, made of an aluminum alloy, are partially formed on the second interlayer insulating film
114
. The third-layer interconnections
117
, which are short-distance interconnections, are relatively short in length. The third-layer interconnections
117
are connected to the second-layer interconnections
113
through the via plugs
116
.
A third interlayer insulating film
118
is formed on the second interlayer insulating film
114
to cover the third-layer interconnections
117
. The third interlayer insulating film
118
is formed of a silicon oxide film or the like. Via holes
119
are formed in the third interlayer insulating film
118
and connected to the third-layer interconnections
117
. The via holes
119
are filled with via plugs
120
made of tungsten or the like. Fourth-layer interconnections
121
, made of an aluminum alloy, are partially formed on the third interlayer insulating film
118
. The fourth-layer interconnections
121
, which are long-distance interconnections or power-supply lines, are relatively long in length. Also, the fourth-layer interconnections
121
are thicker than the first- to third-layer interconnections
109
,
113
and
117
in order to reduce the interconnection resistance and to increase the permissible current density. The fourth-layer interconnections
121
are connected to the third-layer interconnections
117
through the via plugs
120
.
A fourth interlayer insulating film
122
is formed on the third interlayer insulating film
118
to cover the fourth-layer interconnections
121
. The fourth interlayer insulating film
122
is formed of a silicon oxide film or the like. Via holes
123
are formed in the fourth interlayer insulating film
122
and connected to the fourth-layer interconnections
121
. The via holes
123
are filled with via plugs
124
made of tungsten or the like. A fifth-layer interconnection
125
and a bonding pad
126
, both made of an aluminum alloy, are formed partially on the fourth interlayer insulating film
122
. The fifth-layer interconnection
125
, which is a long-distance interconnection or a power-supply line, is relatively long in length. Also, the fifth-layer interconnection
125
is thicker than the first- to third-layer interconnections
109
,
113
and
117
in order to reduce the interconnection resistance and to increase the permissible current density. The fifth-layer interconnection
125
and the bonding pad
126
are connected to the fourth-layer interconnections
121
through the via plugs
124
.
A protective insulating film
127
is formed on the fourth interlayer insulating film
122
to cover the fifth-layer interconnection
125
and the bonding pad
126
. The protective insulating film
127
is formed of a silicon oxide film, a silicon nitride film (Si
3
N
4
), a silicon oxynitride film (SiON), or a composite film thereof. A buffer coat film
128
is formed on the protective insulating film
127
when required. The buffer coat film
128
is made of polyimide or the like.
An opening
129
, having its bottom defined by the bonding pad
126
, is formed in part of the protective insulating film
127
and the buffer coat film
128
. A bonding wire
130
is inserted in the opening
129
and bonded to the bonding pad
126
. The bonding wire
130
is made of gold (Au), aluminum, or the like. A metal layer
131
is formed at the interface between the bonding wire
130
and the bonding pad
126
. When the bonding wire
130
and the bonding pad
126
are made of different materials, the metal layer
131
is a layer of a compound of the material metal of the bonding wire
130
and that of the bonding pad
126
. When the two are made of the same material, the metal layer
131
is an inter-diffusion layer of the material metals.
The buffer coat film
128
and the bonding wire
130
are sealed with a molding resin
132
.
FIGS. 27
to
35
are cross-sectional views showing a sequence of process steps for manufacturing the semiconductor device shown in FIG.
26
. First, referring to
FIG. 27
, the element isolation insulating film
102
is formed in the element isolation region of the silicon substrate
101
by a LOCOS (Local Oxidation of Silicon) isolation or trench isolation process. Next, the MOSFETs
106
are formed in the element formation region of the silicon substrate
101
by known processes such as CVD (Chemical Vapor Deposition), anisotropic dry etching, ion implantation, etc. Next, the underlying insulating film
107
is formed by CVD over the entire surface.
Next, referring to
FIG. 28
, the contact holes
108
are formed in the underlying insula
Izumitani Junko
Takewaka Hiroki
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