Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2002-12-11
2004-08-03
Nguyen, Long (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S108000, C327S112000, C326S081000, C326S083000
Reexamination Certificate
active
06771109
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices. Particularly, the present invention relates to a semiconductor device with interface circuitry whose operating speed is not degraded even when the power supply voltage is of a low level.
2. Description of the Background Art
In accordance with microminiaturization in the semiconductor processing technique, the number of transistors that can be integrated in one chip has drastically increased these few years. At the same time, this implies more stringent requirements with respect to the voltage that can be applied to the transistor. It is inevitable to reduce the power supply voltage in order to suppress power consumption increase reflecting the larger number of integrated transistors. In the case of the most commonly employed MOS transistors, the power supply voltage has become as low as 2.5V, 1.8V and 1.5V as the smallest processing dimension is reduced to 0.25 &mgr;m, 0.18 &mgr;m and 0.15 &mgr;m. The power supply voltages are called the power supply voltage VDD of core circuitry, reflecting their usages at the core portion of the integrated circuitry.
In contrast, the power supply voltage VDDH of interface circuitry serving to transfer a signal with another chip is set to a higher potential level than the power voltage VDD of the core circuitry, irrespective of the progress in the processing technology. In the present state of affairs, power supply voltage VDDH is generally 3.0V to 3.3V. Since the state-of-the-art transistor cannot be used under 3.3V, the transistor of the interface circuitry has the gate oxide film intentionally formed thicker than that of the transistor of the core circuitry, despite the great degradation in performance.
The reason why power supply voltage VDDH of the interface circuitry is set high is set forth below. Firstly, not all the semiconductor devices mounted on the board are fabricated by the most advanced processing technology. There are many semiconductor devices that operate according to the conventional interface standard. Modification of the interface standard will induce considerable turmoil.
The second reason may be due to the close provision of the interface circuitry with respect to the input/output pins. In view of the surge damage of the input/output pins caused by static electricity a thicker gate oxide film is favorable from the standpoint of a higher electrostatic damage resistance (ESD resistance).
In the following, a transistor with a thick gate oxide film is called a thick film transistor whereas a transistor with a thin gate oxide film is called a thin film transistor.
FIG. 14
is a circuit diagram to describe the portion related to data output of a conventional semiconductor device that receives two types of power supply voltages VDD and VDDH for operation.
Referring to
FIG. 14
, a conventional semiconductor device
500
includes core circuitry
501
receiving power supply voltage VDD to operate, and interface circuitry
502
receiving power supply voltage VDDH to operate.
Core circuitry
501
includes a NAND gate G
51
receiving a signal D
0
and an output enable signal EN, an inverter
510
receiving and inverting output enable signal EN, and a NOR gate G
52
receiving the output of inverter
510
and signal D
0
. Each of these circuits included in core circuitry
501
is formed of thin film transistors.
Here, signal D
0
is the output data received from an internal circuit not shown in core circuitry
501
. When output enable signal EN has a logic level of H (logical high), signal D
0
is output as a signal D
1
from the output node of interface circuitry
502
. When output enable signal EN has a logical level of L (logical low), the output node of interface circuitry
502
is set to a high impedance state.
Interface circuitry
502
includes level shift circuits
512
and
514
, and an output drive circuit
516
driving an output node ND
51
according to the signal output from level shift circuits
512
and
514
.
Level shift circuits
512
and
514
receive the outputs of NAND gate G
51
and NOR gate G
52
, respectively, provided from core circuitry
501
to change the potential amplitude of each received signal between core circuitry
501
receiving power supply voltage VDD to operate and output drive circuit
516
receiving power supply voltage VDDH to operate.
Output drive circuit
516
includes an inverter
522
receiving and inverting the signal output from level shift circuit
512
, an inverter
524
receiving and inverting the output of inverter
522
, and a P channel MOS transistor P
51
connected to a power supply node to which power supply voltage VDDH is applied (referred to as power supply node VDDH hereinafter) and output node ND
51
to receive the output of inverter
524
at its gate. Output drive circuit
516
also includes an inverter
526
receiving and inverting the signal output from level shift circuit
514
, an inverter
528
receiving and inverting the output of inverter
526
, and an N channel MOS transistor N
51
connected to output node ND
51
and a ground node to receive the output of inverter
528
at its gate. A capacitance CL
1
is the load capacitance of output node ND
51
.
The operation of semiconductor device
500
will be described here.
When data of an H level is output from semiconductor device
500
, output enable signal EN and signal D
0
are both set to an H level. On the part of P channel MOS transistor P
51
, the output of NAND gate G
51
is driven to an L level, and the output of inverter
524
is driven to an L level. Therefore, P channel MOS transistor P
51
is turned ON.
On the part of N channel MOS transistor N
51
, the output of NOR gate G
52
is driven to an L level, and the output of inverter
528
is driven to an L level. Therefore, N channel MOS transistor N
51
is turned OFF. Accordingly, output node ND
51
is driven to an H level (VDDH), whereby a signal D
1
of an H level is output.
In contrast, when data of an L level is output from semiconductor device
500
, output enable signal EN is set at an H level and signal D
0
is set at an L level. On the part of P channel MOS transistor P
51
, the output of NAND gate G
51
is driven to an H level, and the output of inverter
524
is driven to an H level. Therefore, P channel MOS transistor P
51
is turned OFF.
On the part of N channel MOS transistor N
51
, the output of NOR gate G
52
is driven to an H level, and the output of inverter
528
is driven to an H level. Therefore, N channel MOS transistor N
51
is turned ON. Accordingly, output node ND
51
is driven to an L level (GND), whereby signal D
1
of an L level is output.
When semiconductor device
500
does not output data, output enable signal EN is set at an L level. On the part of P channel MOS transistor P
51
, the output of NAND gate G
51
is driven to an H level, and the output of inverter
524
is driven to an H level. Therefore, P channel MOS transistor P
51
is turned OFF.
On the part of N channel MOS transistor N
51
, the output of NOR gate G
52
is driven to an L level, and the output of inverter
528
is driven to an L level. Therefore, N channel MOS transistor N
51
is also turned OFF. Accordingly, both the two output transistors P
51
and N
51
are turned OFF, whereby output node ND
51
attains a high impedance state.
Reducing power consumption has become a critical issue in accordance with the spread of portable terminals and the like. Power consumption is proportional to the square of the power supply voltage. Therefore, lowering the power supply voltage is extremely effective to reducing power consumption. Although the power supply voltage of the core circuitry has been reduced in accordance with microminiaturization of the semiconductor processing technology, the 3V type is still employed for the interface circuitry as described above, except for particular applications. However, the problem of the slow operating speed of the interface circuitry and power consumption were not so acute thus far.
Corresponding to the need with the increasing dem
McDermott Will & Emery LLP
Nguyen Long
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