Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays
Reexamination Certificate
2002-05-03
2003-12-09
Fahmy, Wael (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
C257S324000
Reexamination Certificate
active
06661040
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technique for realizing high level of integration and increase in capacity of a semiconductor memory device.
2. Description of the Background Art
FIG. 18
is a sectional view illustrating the structure of one cell of a semiconductor memory device
10
P in the background art. The semiconductor memory device
10
P is known as an “NROM”, whose description is given in “Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials, 1999, pp. 522-524”, for example.
The semiconductor memory device
10
P includes a p-type silicon substrate
20
P, an ONO film
30
P (consisting of silicon oxide film
30
AP/silicon nitride film
30
BP/silicon oxide film
30
CP) and a gate electrode
40
P. The ONO film
30
P and the gate electrode
40
P are sequentially provided in this order on the p-type silicon substrate
20
P. The surface of the silicon substrate
20
P includes a pair of n-type layers
51
P and
52
P provided therein. These n-type layers
51
P and
52
P are arranged in the vicinity of the ends of the ONO film
30
P. In the semiconductor memory device
10
P according to the background art, the ONO film
30
P, the gate electrode
40
P and the two n-type layers
51
P,
52
P constitute a cell
10
CP.
In the semiconductor memory device
10
P, bit judgment is performed on the basis of whether a portion
30
B
1
P in the nitride film
30
BP defined in the vicinity of the n-type layer
51
P includes electrons and further, on the basis of whether a portion
30
B
2
P in the nitride film
30
BP defined in the vicinity of the n-type layer
52
P includes electrons. That is, the cell
10
CP of the semiconductor memory device
10
P serves as a device for storing 2 bits of information.
More particularly, when a positive voltage is applied to the gate electrode
40
P using the n-type layer
51
P as a source and using the n-type layer
52
P as a drain, a gate threshold voltage of a driving current changes on the basis of whether the portion
30
B
1
P in the nitride film
30
BP includes electrons. Conversely, when a positive voltage is applied to the gate electrode
40
P using the n-type layer
51
P as a drain and using the n-type layer
52
P as a source, a gate threshold voltage of a driving current changes on the basis of whether the portion
30
B
2
P in the nitride film
30
BP includes electrons.
SUMMARY OF THE INVENTION
In response to the need in recent years for higher level of integration and increase in capacity to a greater degree of a semiconductor memory device, it is an object of the present invention to provide a semiconductor memory device realizing higher level of integration and increase in capacity to a greater degree as compared with the semiconductor memory device
10
P in the background art.
According to the present invention, the semiconductor memory device includes a semiconductor substrate of a first conductivity type having a substrate surface, a first gate insulating film, a first gate electrode and at least four impurity layers each being of a second conductivity type opposite to the first conductivity type. The first gate insulating film is provided on the substrate surface and capable of accumulating electric charges. The first gate electrode is provided on the substrate surface through the first gate insulating film. The at least four impurity layers are provided in the substrate surface to surround the first gate insulating film in a plan view of the substrate surface.
In the semiconductor memory device, in the plan view of the substrate surface, the at least four impurity layers form a plurality of first pairs and each of the plurality of first pairs includes impurity layers opposed to each other through the first gate insulating film. Each of the plurality of first pairs serves as a source/drain of a MISFET structure including the semiconductor substrate, the first gate insulating film and the first gate electrode.
In the semiconductor memory device, the semiconductor memory device includes a plurality of (or at least two) MISFET structures provided to each first gate insulating film and first gate electrode (namely, in one cell). Therefore, as compared with the semiconductor memory device in the background art including only one MISFET structure in one cell, the number of bits to be stored in one cell is increased. As a result, it is possible to realize higher level of integration and increase in capacity to a greater degree.
Preferably, the semiconductor memory device includes a second gate insulating film, a second gate electrode and at least two impurity layers each being of the second conductivity type. The second gate insulating film is provided on the substrate surface and capable of accumulating electric charges. The second gate electrode is provided on the substrate surface through the second gate insulating film. The at least two impurity layers are provided in the substrate surface to surround the second gate insulating film together with part of the at least four impurity layers in the plan view of the substrate surface.
In the semiconductor memory device, in the plan view of the substrate surface, the at least two impurity layers and the part of the at least four impurity layers form a plurality of second pairs and each of the plurality of second pairs includes impurity layers opposed to each other through the second gate insulating film. Each of the plurality of second pairs serves as a source/drain of a MISFET structure including the substrate surface, the second gate insulating film and the second gate electrode.
In the semiconductor memory device, the MISFET structure (or cell) (including the first gate insulating film and the first gate electrode) and the MISFET structure (or cell) (including the second gate insulating film and the second gate electrode) share part of at least four impurity layers. Therefore, as compared with the structure including the cells each having the at least four impurity layers, higher level of integration is realized.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4737837 (1988-04-01), Lee
patent: 5331192 (1994-07-01), Kudoh
patent: 5436481 (1995-07-01), Egawa et al.
patent: 5808330 (1998-09-01), Rostoker et al.
patent: 5-326884 (1993-12-01), None
patent: 7-193151 (1995-07-01), None
patent: WO-00/60665 (2000-10-01), None
Boaz Eitan, et al., “Can NROM, a 2 Bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?”, Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials, Tokyo, 1999, C-11-1, pp. 522-524.
Fahmy Wael
Mitsubishi Denki & Kabushiki Kaisha
Weiss Howard
LandOfFree
Semiconductor device with insulating gate surrounded by... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device with insulating gate surrounded by..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device with insulating gate surrounded by... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3174544