Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2001-05-23
2002-06-11
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S750000, C257S774000
Reexamination Certificate
active
06404055
ABSTRACT:
The present application claims priority under 35 U.S.C. §119 to Korean Application No. 2000-65258 filed on Nov. 3, 2000, which is hereby incorporated by reference in its entirety for all purposes.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device with metal interconnection and a method for forming metal interconnections of a semiconductor device, and more particularly, to a semiconductor device with double damascene metal interconnections and a method for forming the metal interconnections of a semiconductor device.
2. Description of the Related Art
With the increase in integration density of semiconductor devices, conductive layers for a semiconductor device have been deposited on a wafer with a multi-level structure. The multi-level interconnection structure contributes to reducing the cell area and design rule of the semiconductor device, thereby increasing the integration density of the semiconductor device. For multi-level interconnections having smaller size, it would be desirable to conduct extensive research and development into advanced metal interconnection structures and alternative materials used to form interconnections.
A double damascene technique has been used to form advanced interconnections. According to the double damascene technique, a trench aligned with a gate electrode and a via hole through which a selected junction area is exposed are formed, and both the trench and the via hole are filled with a conductive material by the same process. Thus, the double damascene technique is advantageous because it simplifies the entire metal interconnection process.
A structure of metal interconnection of a semiconductor device manufactured using a conventional double damascene technique is shown in FIG.
1
.
FIG. 2
is a plan view of the metal interconnection shown in FIG.
2
. Referring to
FIGS. 1 and 2
, a gate insulating layer
21
and a conductive layer for forming a gate electrode is deposited in succession on a semiconductor substrate
20
having a first conductive type. A selected portion of the conductive layer is patterned into a gate electrode
23
. Spacers
25
are formed on the sidewalls of the gate electrode
23
by a known technique. Impurities having a second conductive type, which is an opposite type to that of the semiconductor substrate
20
, are implanted into substrate
20
on both sides of the gate electrode
23
, thereby forming junction area
27
.
A first interlevel dielectric (ILD) film
29
is formed over the semiconductor substrate
20
having the gate electrode
23
and the junction area
27
, to a thickness of 8,000-20,000 Å. Following this, the surface of the first ILD film
29
is polished a predetermined depth by chemical mechanical polishing. A selected portion of the first ILD film
29
is patterned to form a trench T aligned with the gate electrode
23
, and a via hole H through which the junction area
27
between adjacent gate electrodes is exposed. Here, a selected portion of the first IDL film
29
is removed by etching to form the trench T, such that the depth of the trench T is smaller than the depth of the via hole H.
Following this, an adhesive layer
31
is deposited along the surface of the first ILD film
29
and in the via hole H and the trench T, and a metal layer
32
is thereafter deposited on the structure to fill the via hole H and the trench T. The metal layer
32
and the adhesive layer
31
are polished by chemical mechanical polishing until the surface of the first ILD film
29
is exposed. As a result, first metal interconnections
34
a
and
34
b
having the metal layer
32
and the adhesive layer
31
embedded in the via hole H and the trench T are completed. In this case, since the first metal interconnection
34
b
formed in the trench T are aligned with the gate electrode
23
, a series of first metal interconnections
34
b
are arranged in lines parallel to each other over the substrate
20
, separated by a predetermined distance from each other, as shown in FIG.
2
.
Next, a second ILD film
36
is deposited over the first ILD film
29
including the first metal interconnections
34
a
and
34
b
therein, and then the second ILD film
36
is partially etched such that the first metal interconnection
34
a
filling the via hole H is exposed. A second metal interconnection
38
is formed over the second ILD film
29
such that the second metal interconnection
38
contacts the first metal interconnection
34
a,
which is exposed by etching. The second metal interconnection
38
is formed to be perpendicular to the first metal interconnection
34
b
filling the trench T, as shown in FIG.
2
.
However, there are problems in forming metal interconnections by the conventional double damascene technique. Chemical mechanical polishing causes aggregations of slurry that is applied as an abrasive, and polishing residues, (not shown) to remain on the polished surface of a layer. As a result, when physical force is applied through a polishing pad to polish the first ILD film
29
for example, the surface of the first ILD film
29
is scratched due to the presence of such slurry aggregations and polishing residues. Scratches on the surface of the first ILD film
29
, which are caused by the slurry aggregations and polishing residues, are referred to as “microscratches”. As shown in
FIG. 2
, microscratches
39
occur in lines in a polishing direction. The depth of the microscratches
39
vary depending on the force applied to the polishing pad and the particle size of the slurry aggregates and polishing residues. Usually, the depth of the microscratches
39
are in the range of 500-1500 Å, but if serious, can be as deep as 2000 Å.
During formation of the first metal interconnections
34
a
and
34
b,
portions of the adhesive layer
31
and the metal layer
32
remain caught in the unnecessary microscratches formed on the first ILD film
29
. As shown in
FIG. 2
, since the microscratches
39
occur in lines along a polishing direction, the remaining metal layer
32
serves as bridges between adjacent first metal interconnections
34
a
and
34
b,
as shown in
FIGS. 3 and 4
, thereby causing a short between the first metal interconnections
34
a
and
34
b.
As a result, failure occurs during the manufacture of semiconductor devices, thereby degrading the electrical properties of semiconductor devices.
SUMMARY OF THE INVENTION
The present invention is therefore directed to a semiconductor device with improved metal interconnection, and a method of forming the metal interconnection, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.
To solve the above problems, it is a first object of the present invention to provide a semiconductor device with improved metal interconnections, which does not include shorts between adjacent metal interconnections.
It is a second object of the present invention to provide a method for forming metal interconnections of a semiconductor device, which is capable of preventing the occurrence of shorts between the metal interconnections formed using a double damascene technique.
The first and other objects of the present invention are achieved by a semiconductor device with an improved metal interconnection structure, including a substrate in which a plurality of conductive areas are defined, and an interlevel dielectric (ILD) film with a polished surface that covers the substrate and that has a via hole and a trench with a smaller depth than the via hole. Here, a selected conductive area is exposed through the via hole. The semiconductor device also includes a metal interconnection formed in each of the via hole and the trench, and an anti-short insulating layer formed on the sidewalls of the metal interconnection formed in the trench.
The anti-short insulating layer may be further formed on the bottom of the trench filled with the metal interconnection, and on the surface of the ILD film adjacent to the trench. The anti-short insulating layer
Jeon Jeong-sic
Kim Jae-woong
Kim Sang-hee
Volentine & Francos, PLLC
Wilson Allan R.
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