Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-11-08
2004-04-20
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185080, C365S154000
Reexamination Certificate
active
06724657
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having electrically erasable and rewritable nonvolatile memory transistors; and, more specifically, the invention relates to a technique that is applicable to a semiconductor device having nonvolatile memories, which uses flip-flops (nonvolatile memory circuits) including plural nonvolatile memory transistors as a storage unit.
A flash EEPROM memory has been provided as a nonvolatile memory, which is capable of electrically erasing data as well as electrically writing data collectively in a specific unit, which memory is hereunder referred to as a flash memory. The flash memory has memory cells configured with electrically erasable and writable nonvolatile memory transistors, which memory is capable of erasing data and programs that are written temporarily in memory cells and rewriting new data and programs in the memory cells.
Therefore, after integrating the flash memory or a microcomputer containing the flash memory into an application system, when modifications of data, corrections of bugs in a program, and updates of the program, and the like become necessary, the data and programs stored in the flash memory can be modified on the application system, which accordingly achieves a reduction of the development term of the application system and gives flexibility to the program development of the application system.
Recently, on the other hand, a system semiconductor device has been provided, in which a central processing unit (Hereunder, also referred to as a CPU) operating as a data control device, a DRAM (Dynamic Random Access Memory) serving as a large scale memory, an SRAM (Static Random Access Memory) serving as a high speed memory or a cache memory, and other functional circuits are integrally formed on one semiconductor substrate (hereunder, also referred to as a system LSI), whereby one semiconductor device can form one complete system. This type of system LSI contributes to a size reduction of a PCB and a packaging substrate, and exhibits a significant effect in miniaturization and weight reduction of portable equipment, such as portable telephones, portable data terminals, and the like.
The inventors of the present invention have examined the prior art from the following aspect A and aspect B.
The aspect A involves provision of nonvolatile memory transistors with single layer polysilicon gates, and the aspect B involves the use of flip-flops, including the nonvolatile memory transistors, as a storage unit.
As a result, the inventors have discovered, with regard to aspect A, the U.S. Pat. No. 5,440,159, the U.S. Pat. No. 5,504,706, Japanese Unexamined Patent Publication No. Hei 4 (1992)1212471 (corresponding to U.S. Pat. No. 5,457,335), and a thesis by Osaki et al. on “A single poly EEPROM Cell Structure for use in Standard CMOS Processes” published in the IEEE Journal of Solid-state Circuits, VOL. 29, No. 3, March 1994, pp 311-316.
On the other hand, the inventors discovered, with regard to aspect B, Japanese Unexamined Patent Publication No. Hei 5(1993)-314789, Japanese Unexamined Patent Publication No. Hei 6(1994)-76582, and Japanese Unexamined Patent Publication No. Hei 10(1998)-334691 (corresponding to U.S. Pat. No. 5,912,841). The Japanese Unexamined Patent Publication No. Hei 5(1993)-314789 discloses a technique in which two electrically rewritable nonvolatile memory (EPROM) transistors are constructed by using flip-flops composed of a drive transistor and two load transistors as a storage unit, and in which redundant addresses of a relief circuit are stored.
SUMMARY OF THE INVENTION
The inventors' examination of the foregoing documents revealed the following points. First of all, the first problem discovered by the inventors was that, in the flip-flop circuit composed of the drive transistor (nonvolatile memory transistor) and the two load transistors, as disclosed in the Japanese Unexamined Patent Publication No. Hei 5(1993)-314789, the initial threshold voltage in which the floating gates do not hold any charges at all, the threshold voltage in the writing/erasing state, and the word line potential in reading greatly influence the rate of occurrence of readout errors resulting from a deterioration of the charge holding characteristics.
FIG. 25
shows a flip-flop circuit including the nonvolatile memory transistor that the inventors examined, illustrating a state in which writing is executed to one nonvolatile memory transistor
223
, and, thereafter, the reading is executed by applying the supply voltage Vcc to the supply line. In
FIG. 25
, reference numerals
220
and
221
denote a p-channel load transistor; and reference numerals
222
and
223
denote an n-channel nonvolatile memory transistor. Since the one transistor
222
of the two nonvolatile memory transistors has the initial threshold voltage (VthL) and the other transistor
223
has the high threshold voltage (VthH), while the potential of the power supply line rises from 0 Volt to the power supply voltage Vcc, the latch is locked; and, accordingly, Vcc (H level) is applied to the drain of the nonvolatile memory transistor
223
having the high threshold voltage (VthH) and to the gate of the nonvolatile memory transistor
222
having the initial threshold voltage (VthL) acting as the so-called disturbing voltage. In this state of disturbance, a stress acts in a direction such that the charges stored in the floating gate of the nonvolatile memory transistor
223
having the high threshold voltage (VthH) are pulled out toward the drain terminal; on the other hand, a stress acts in the direction such that the charges are poured into the floating gate of the nonvolatile memory transistor
222
having the initial threshold voltage (VthL). Since the semiconductor device is designed on the premise that it operates continuously for ten years, it has to be considered that the stresses which act on the nonvolatile memory transistors
222
,
223
are applied continuously for ten years. Therefore, the rise of the threshold voltage in the nonvolatile memory transistor
222
having the initial threshold voltage (VthL), namely the charge gain, and the fall of the threshold voltage in the nonvolatile memory transistor
223
having the high threshold voltage (VthH), namely the charge loss, occur at the same time. In case a gate oxide film is made thin, the threshold voltages of the two nonvolatile memory transistors
222
,
223
approach an equal value comparably easily, and it is believed that a readout error occurs due to a conversion of latched data. Thus, the inventors discovered that the flip-flop circuit with the supply voltage Vcc always applied as shown in
FIG. 25
is not resistant to the disturbing voltage.
The second problem discovered by the inventors is that, in the vertically stacked-structure comprising memory cells of the floating gates and the control gates, namely the stacked gate memory cells, the complicated memory cell structure increases the manufacturing cost. Especially, in the so-called system LSI product that incorporates the flash memory, which has experienced rapid growth in the market in recent years, together with high-speed logic circuits, a DRAM, and the like, the application of the stacked memory cells to the flash memory leads to an increase in the manufacturing cost. The investigation by the inventors finds that this is caused by an increase in the number of photo masks and the manufacturing processes. That is, the tunnel oxide film of a flash memory is thicker than the gate oxide film of a logic circuit transistor or the gate oxide film of a DRAM cell transistor. This requires a mask for separately manufacturing a tunnel oxide film, a mask for adding a polysilicon film for the floating gate of the flash memory, a mask for processing word lines of the flash memory, an impurity injection mask for forming a drain region of the flash memory, and the impurity injection mask for forming a low density N-type source/drain region and a low density P-type source/drain region for high withstand vo
Antonelli Terry Stout & Kraus LLP
Hoang Huan
Renesas Technology Corp.
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