Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
1999-02-19
2001-05-01
Hardy, David (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S500000
Reexamination Certificate
active
06225676
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a semiconductor device, and more particularly, to the inter-element isolation of a semiconductor device having circuits or elements mounted thereon which operate at a high frequency.
A plurality of elements or circuits are mounted on a single chip in order to achieve a higher level of integration, multiple functions, reduced cost and a reduction in size. To reduce the influences of these circuit elements on each other, an inter-element isolation region is formed between the elements. In one technique of providing inter-element isolation, an isolation region located between circuit elements is directly connected to the ground ohmically, thus stabilizing the potential of the isolation region. In another technique, an insulator is interposed between circuit elements and serves as an isolation region that electrically separates adjacent elements from each other.
However, the above-described inter-element isolation techniques fail to pay adequate consideration to high frequency circuits. Thus, there is insufficient isolation between circuits or elements with high frequency signals, allowing mutual interference to occur between the high frequency signals, which causes unstable operation of the semiconductor device.
It is an object of the invention to provide a semiconductor device which operates at a high frequency in a stable manner.
SUMMARY OF THE INVENTION
To achieve the above objective, the present invention provides a semiconductor device comprising: a substrate portion of a predetermined conductivity type connected to a ground; a semiconductor layer disposed on the substrate portion, the semiconductor layer including a plurality of island regions and a corresponding plurality of isolation regions that surround the respective island regions for electrically separating island regions from each other, wherein each of the island regions includes a circuit capable of providing a predetermined function; and a first capacitor having a first terminal connected to either the substrate portion or the semiconductor layer and a second terminal connected to the ground.
The present invention further provides a semiconductor device comprising: a substrate portion of a predetermined conductivity type connected to a ground; and a semiconductor layer disposed on the substrate portion and including a plurality of island regions and an isolation region for electrically separating the adjacent island regions from each other, wherein each of the island regions contains a circuit capable of providing a predetermined function, and the isolation region includes a conductive region having a conductivity type opposite to the substrate portion conductivity type, wherein a parasitic capacitor is formed between the substrate portion and the conductive region.
The present invention provides a semiconductor device comprising: a substrate portion of a predetermined conductivity type connected to a ground; a semiconductor layer disposed on the substrate portion and including a plurality of island regions and an isolation region for electrically separating adjacent island regions from each other, wherein each of the island regions contains a circuit capable of providing a predetermined function, and the isolation region includes a conductive region having a conductivity type opposite to the substrate portion conductivity type; and an embedded layer of a higher concentration of impurities than the conductive region and disposed between the substrate portion and the conductive region, a parasitic capacitor being formed between the substrate portion and the embedded layer and having a capacitance that depends on the impurity concentration of the embedded layer.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 5055905 (1991-10-01), Anmo
patent: 5805410 (1998-09-01), Lee
patent: 5939753 (1999-08-01), Ma et al.
patent: 6104094 (2000-08-01), Ban et al.
Hattori Yoshinobu
Saito Shinji
Tsukahara Masahiro
Armstrong Westerman Hattori McLeland & Naughton LLP
Fujitsu Limited
Hardy David
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