Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – Plural non-isolated transistor structures in same structure
Reexamination Certificate
2001-01-17
2002-06-04
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
Plural non-isolated transistor structures in same structure
C257S254000
Reexamination Certificate
active
06399999
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device such as lateral bipolar transistor and diode.
2. Description of Related Art
FIG. 5
is a plan view showing a conventional semiconductor device, for example, a lateral bipolar transistor as shown in Japanese Patent No. 2,665,820, and
FIG. 6
is a front view in section taken along the line II—II of FIG.
5
. In
FIGS. 5 and 6
, reference numeral
1
designates a semiconductor substrate;
2
designates an n+ type buried layer;
3
designates an epitaxial layer;
4
designates a device isolation region;
5
designates a base diffusion region;
6
designates an emitter diffusion region;
7
designates a collector diffusion region;
8
designates an insulating oxide, which is an insulating layer;
9
,
10
, and
11
each designate a contact hole;
12
designates a wiring layer for a base electrode;
13
designates an emitter electrode wiring layer;
14
designates a collector electrode wiring layer;
15
designates a hole;
16
designates an electron; and
17
designates an interlayer dielectric.
Here, the lateral bipolar transistor is that the emitter, base, and collector are formed on the same surface as that of a substrate crystal, and components in parallel to the surface of the flow of minor careers which are injected from the emitter dominate the operation of the transistor.
The operation will be next described below.
Typically, under such a condition that a reverse bias voltage is applied to the collector of the lateral transistor, the potential of the emitter is lowered, while the potential applied to the collector diffusion layer
7
is raised. Thus, when the voltage difference between the collector and the emitter is made larger than a reverse breakdown voltage BV
EOC
, there are some occasions that a current flows out from the collector diffusion layer
7
to the emitter diffusion layer
6
. In the example of
FIGS. 5 and 6
, however, since the collector diffusion layer
7
is separated under the emitter electrode wiring layer
13
, there are no current flows from the collector diffusion layer
7
to the emitter diffusion layer
6
.
However, in the example of
FIGS. 5 and 6
, when the emitter electrode wiring layer
13
has a lower potential than that of the collector diffusion layer
7
, and the application voltage of the collector diffusion layer
7
is raised to reach the reverse breakdown voltage BV
EOC
, an inversion layer (hole
15
) is formed on the surface of the epitaxial layer
3
, which is positioned under the emitter electrode wiring layer
13
. For this reason, a leakage current from the emitter diffusion layer
6
occurs and flows out to the device isolation region
4
.
Since the conventional semiconductor device is configured as described above, a leakage current occurs from the emitter diffusion layer
6
under such a condition that a reverse bias is applied to the collector of the lateral transistor, and further the leakage current flows out to the device isolation region
4
, causing increased consumption power, device malfunctions, and so on. Thus, the operation range of the device cannot be enlarged.
SUMMARY OF THE INVENTION
The present invention is implemented to solve the foregoing drawbacks. It is therefor an object of the present invention to provide a semiconductor device which is capable of preventing the occurrence of a leakage current from the emitter diffusion layer to the device isolation region, even under such a condition that a reverse bias is applied to the collector.
According to a first aspect of the present invention, there is provided a semiconductor device comprising: an epitaxial layer formed on a semiconductor substrate; a device isolation region formed with a predetermined surrounding frame pattern in the epitaxial layer; an emitter diffusion layer and a collector diffusion layer which are formed in the surface area of the epitaxial layer in the device isolation region, a frame pattern of the collector diffusion layer being laid out in a fashion to surround the emitter diffusion layer; an insulating layer formed on the epitaxial layer; an emitter electrode wiring layer that is led from the emitter diffusion layer through a first contact hole opened in the insulating layer; a collector electrode wiring layer that is led from the collector diffusion layer through a second contact hole opened in the insulating layer; and a control wiring layer which is laid down under the emitter electrode wiring layer, and which is applied a voltage according to a reverse bias voltage to be applied to the collector diffusion region.
Here, it is preferable that the control wiring layer is be arranged on the insulating layer that is formed on the surface of the epitaxial layer, and that an interlayer dielectric is formed between the control wiring layer and the emitter electrode wiring layer.
In addition, the semiconductor device may further comprise a base diffusion layer laid out on the outer surface area of the collector diffusion layer, and a base electrode wiring layer that is led from the base diffusion layer through a third contact hole opened in the insulating layer in the device isolation region.
Further, a voltage not less than a reverse bias voltage applied to the collector diffusion layer may be applied to the control wiring layer.
Alternatively, a voltage less than a reverse bias voltage applied to the collector diffusion layer is applied to the control wiring layer.
Furthermore, the base electrode wiring layer may be connected to the collector electrode wiring layer.
REFERENCES:
patent: 5554872 (1996-09-01), Baba et al.
patent: 5592015 (1997-01-01), Iida et al.
patent: 6054752 (2000-04-01), Hara et al.
patent: 59-151460 (1984-08-01), None
patent: 2-220445 (1990-09-01), None
patent: 2665820 (1997-06-01), None
Burns Doane , Swecker, Mathis LLP
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
Nguyen Thinh T
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