Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With specified crystal plane or axis
Reexamination Certificate
2007-03-27
2007-03-27
Soward, Ida M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With specified crystal plane or axis
C257S062000, C257S063000, C257S065000, C257S255000, C257S521000, C257S527000, C257S616000, C257S628000
Reexamination Certificate
active
10835077
ABSTRACT:
An object is to enhance the orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film while using as a substrate a less-heat-resistive material such as glass thereby providing a semiconductor device using a crystalline semiconductor film with high quality equivalent to a single crystal. A first crystalline semiconductor film and a second crystalline semiconductor film are formed overlying a substrate, which integrally structure a crystalline semiconductor layer. The first and second crystalline semiconductor films are polycrystalline bodies aggregated with a plurality of crystal grains. However, the crystal grains are aligned toward a (101)-plane orientation at a ratio of 30 percent or greater, preferably 80 percent or greater. Also, relying on a plane orientation of the crystal grains in the first crystalline semiconductor film, the second crystalline semiconductor film has a plane orientation also aligned in the same direction with a probability of 60 percent or higher.
REFERENCES:
patent: 5643826 (1997-07-01), Ohtani et al.
patent: 5700333 (1997-12-01), Yamazaki et al.
patent: 5773847 (1998-06-01), Hayakawa
patent: 5789284 (1998-08-01), Yamazaki et al.
patent: 5923962 (1999-07-01), Ohtani et al.
patent: 5932893 (1999-08-01), Miyanaga et al.
patent: 6013544 (2000-01-01), Makita et al.
patent: 6048780 (2000-04-01), Hayakawa
patent: 6140165 (2000-10-01), Zhang et al.
patent: 6261705 (2001-07-01), Tanikawa et al.
patent: 6326226 (2001-12-01), Jang et al.
patent: 6337224 (2002-01-01), Okamoto et al.
patent: 6388270 (2002-05-01), Yamazaki et al.
patent: 6475840 (2002-11-01), Miyanaga et al.
patent: 6583776 (2003-06-01), Yamazaki et al.
patent: 6624051 (2003-09-01), Ohtani et al.
patent: 6693044 (2004-02-01), Yamazaki et al.
patent: 6828587 (2004-12-01), Yamazaki et al.
patent: 7098508 (2006-08-01), Ieong et al.
patent: 2002/0008286 (2002-01-01), Yamazaki et al.
patent: 2002/0013114 (2002-01-01), Ohtani et al.
patent: 2002/0036289 (2002-03-01), Tamura et al.
patent: 2002/0038889 (2002-04-01), Yamazaki et al.
patent: 2002/0043660 (2002-04-01), Yamazaki et al.
patent: 2002/0043662 (2002-04-01), Yamazaki et al.
patent: 2002/0163035 (2002-11-01), Yamazaki
patent: 07-130652 (1995-05-01), None
patent: 07-231100 (1995-08-01), None
patent: 08-078329 (1996-03-01), None
patent: 09-082639 (1997-03-01), None
patent: 11-204435 (1999-07-01), None
patent: 2000-114172 (2000-04-01), None
U.S. Appl. No. 09/227,577 filed Jan. 8, 1999; Yamazaki et al. “Semiconductor Device and Method of Manufacturing the Same”.
Kasahara Kenji
Mitsuki Toru
Yamazaki Shunpei
Costellia Jeffrey L.
Nixon & Peabody LLP
Semiconductor Energy Laboratory Co,. Ltd.
Soward Ida M.
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