Semiconductor device with efficiently arranged pads

Details Semiconductor device with efficiently arranged pads Semiconductor device with efficiently arranged pads

1997-07-25

2002-10-22

Wille, Douglas A. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular power supply distribution means

C257S208000

Reexamination Certificate

active

06469327

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and particularly to efficient arrangement of pads on a semiconductor chip. More specifically, it relates to a configuration implementing testability and stable supply of an internal power-supply potential while employing such pad arrangement.
2. Description of the Background Art
FIG. 15
schematically shows a chip layout of a semiconductor device having a conventional pad arrangement suitable for a LOC (Lead on Chip) structure. In
FIG. 15
, pads PD are alignedly arranged on a central region CR with respect to a second direction (referred to as “the shorter side direction” hereinafter), extending in a first direction (referred to as “the longer side direction” hereinafter) of a semiconductor chip
1
. Arranged at each side of central region CR of semiconductor chip
1
are internal circuits M#0-M#3 which, for example, are memory cell arrays. Pad PD is connected through a bonding wire to a lead frame FR extending over the semiconductor chip to the central portion near central region CR.
With this LOC structure, it is possible to alignedly arrange the pads PD in a line in central region CR. Therefore, compared with the configuration in which the pads are arranged at both end portions in the shorter side direction, the pad occupying area can be reduced and accordingly, the chip area can be reduced. Furthermore, since the pads, serving as interface of signals and voltages (power-supply potential and ground potential), are arranged in central region CR, the length of a interconnection line such as a signal line and a power-supply line to internal circuits M#0-M#3 can be reduced, signal propagation delay can be reduced and interconnection layout is relatively facilitated. Also, since pads PD are alignedly arranged in a line, probes for testing the semiconductor device can be alignedly arranged in a line and according to the pitch of pads PD in a wafer test. Accordingly, a number of probes can be arranged in parallel in the measuring jig and the number of semiconductor devices (chips) which can simultaneously be observed can be increased.
In the recent semiconductor devices, particularly, in the semiconductor memory device, the number of input/output data bits has been increased to 16 bits, 32 bits, and so on and the number of input/output data pads is accordingly increased. Furthermore, with the multi-functionalization of semiconductor devices, a variety of tests have to be performed a number of times to ensure reliability of the semiconductor devices, and a monitor pad for outputting externally a signal indicating an internal state when the tests are performed is required. Since the number of pads which can be arranged in central region CR is determined by the longer side length of semiconductor chip
1
, it is difficult to alignedly arrange all of a number of pads in a line in central region CR without increasing the longer side length of the chip.
Furthermore, in a integrated semiconductor memory device, the operating power-supply potential is lowered to reduce power to be consumed and to enable high-speed operation. On the other hand, a device such as CPU (Central Processing Unit) serving as an external device has a smaller integration degree as compared with the semiconductor memory device and its operating power-supply potential cannot be lowered to that of the semiconductor memory device. Therefore, in the semiconductor memory device, an externally applied potential is internally down-converted to produce a lower power-supply potential in order to maintain its compatibility with an external device and a past-generation semiconductor memory device (a semiconductor memory device with a higher power-supply potential).
FIG. 16
schematically shows the configuration of a conventional internal voltage-down converter used in a semiconductor memory device. In
FIG. 16
, an internal voltage-down converter VDC includes: a drive transistor DR which is connected between a node
2
supplying an external power-supply potential Vcc and an internal power-supply line
3
and is configured by a p channel MOS transistor (an insulated gate type field effect transistor); and a comparison circuit CP which compares a reference potential Vref with an internal power supply potential Vint to control the conductance of drive transistor DR according to the result of the comparison. Comparison circuit CP outputs a high level signal to turn off drive transistor DR when internal power supply potential Vint is higher than reference potential Vref. Reversely, comparison circuit CP outputs a low level signal to increase the conductance of drive transistor DR when internal power supply potential Vint is lower than reference potential Vref. Drive transistor DR supplies current from external power supply node
2
to internal power supply line
3
according to an output signal of comparison circuit CP. Thus, internal power supply potential Vint is maintained at the potential level of reference potential Vref. When an internal circuit operates and consumes internal power supply potential Vint, drive transistor DR supplies a large current from external power supply node
2
to internal power supply line
3
to compensate for the decrease in internal power supply potential Vint.
When such a large current flows, a substrate current can flow from an impurity region of drive transistor DR into the semiconductor substrate and minority carriers can be generated in the semiconductor substrate. When internal circuits M#0-M#3 shown in
FIG. 15
are memory cell arrays, the minority carriers thus generated in the semiconductor substrate may destroy data of memory cells contained in the memory cell arrays and therefore, internal voltage-down converter VDC is preferably arranged as far from the memory cell arrays as possible. In the arrangement shown in FIG.
15
,the farthest portion from such memory cell arrays is central region CR. However, as a number of pads PD are provided in central region CR, it is difficult to further arrange internal voltage-down converter VDC efficiently within central region CR.
Further, if external power supply node
2
is distant from drive transistor DR, that is, if an external power supply pad is distant from internal voltage-down converter VDC, impedance (indicated by the reference character Z) of the external power supply interconnection line is increased, change in current supplied by drive transistor DR is delayed from the change in internal power supply potential Vint on internal power supply line
3
and internal power supply potential Vint cannot be maintained accurately at the level of reference potential Vref. Furthermore, the increased impedance Z produces potential drop on the external power supply interconnection line (the interconnection line between node
2
and drive transistor DR), the conductance of drive transistor DR becomes higher than the designed value (drive transistor DR is a p channel MOS transistor and its conductance is determined by a potential difference between the source and the gate), a required current cannot be supplied onto internal power supply line
3
, the potential drop of internal power supply potential Vint cannot be compensated for, and internal power supply potential Vint cannot be maintained at a constant level of reference potential Vref.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device having an efficient arrangement of pads in which the number of pads can be easily increased without increasing chip size.
Another object of the present invention is to provide a semiconductor device allowing an internal potential generating circuit to be arranged without reducing the number of pads.
Still another object of the present invention is to provide a semiconductor device having an efficient arrangement of pads with which tests can be performed efficiently.
A semiconductor device according to a first aspect of the present invention includes: a plurality of power supply pads each re

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