Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
1999-06-23
2001-01-30
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S112000, C438S458000, C438S460000
Reexamination Certificate
active
06180435
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to assembling technologies for a semiconductor device and, more particularly, to a semiconductor device with an economical compact package and a process for assembling a semiconductor device.
DESCRIPTION OF THE RELATED ART
Various kinds of package are used for semiconductor devices. A tape ball grid array packages, a plastic ball grid array package, a fine pitch ball grid array package and a chip size package are examples of known packages. A surface-mounting package such as the plastic ball grid array package and the chip size package has a ball grid array directly connected to a circuit board, and is appropriate for miniature electric products.
A typical example of the prior art process for the surface-mounting package is illustrated in
FIGS. 1A
to
1
E. First, an insulating plate
1
is prepared.
The insulating plate
1
is a sheet of glass fiber reinforced epoxy resin, which is called as “glass-epoxy substrate”, or is a polyimide tape. Though not shown in the
FIG. 1A
, a conductive pattern of copper is repeatedly formed in small regions on the major surface of the insulating plate
1
, and the small regions are arranged in matrix. Plural semiconductor chips
2
are bonded to the small regions of the insulating plate
1
, and the conductive pattern in a each small region is electrically connected through conductive wires to bonding pads of the associated semiconductor chip
2
.
The semiconductor chips
2
arranged on the insulating plate
1
are placed in a molding die (not shown), and synthetic resin is introduced into the cavities of the molding die. The semiconductor chips
2
are scaled with pieces of the synthetic resin, respectively, and the pieces of synthetic resin serve as the plastic packages
4
. The insulating plate
1
is taken out from the molding die, and is to be cut into the prior art semiconductor devices
5
along dot-and-dash lines shown in
FIG. 1B
as will be described hereinlater. The cutting lines define square substrates
1
a
, and the square substrate
1
a
is wider than the plastic package
4
. In other words, a margin
1
b
is given to the square substrate
1
a.
The insulating plate
1
is conveyed to a cutting machine. The cutting machine has a die unit
12
, and an upper die
12
a
and a lower die
12
b
form in combination the die unit
12
(see FIG.
1
C). The upper die
12
a
has a punch
12
c
, and the punch
12
c
is slidable along holes formed in a guide member
12
d
. The holes are separated from one another by means of pads
12
e
so as to locate the punch
12
c
along the dot-and-dash lines. On the other hand, the lower die
12
b
has a die portion
12
f
connected by means of pads
12
f
. Holes are also formed in the die portions
12
f
, and are respectively aligned with the holes formed in the guide members
12
d
. The upper die
12
a
is spaced from the lower die
12
b
, and the insulating plate
1
is inserted into the gap between the upper die
12
a
and the lower die
12
b
as shown in FIG.
1
C.
The upper die
12
a
is downwardly moved, and the insulating plate
1
is pinched between the guide member
12
d
and the die portion
12
f
as shown in FIG.
1
D. The punch
12
c
is pressed against the insulating plate
1
, and cuts the insulating plate
1
into the square substrates
1
a
as shown in FIG.
1
E.
As described hereinbefore, the insulating plate
1
is formed of the glass fiber reinforced epoxy resin or polyimide. In order to cut the insulating plate into the square substrates
1
a
, it is necessary to pinch the insulating plate
1
between the guide members
12
d
and the die portions
12
f
, and the area to be pinched is wider than the cross section of the punch
12
c
. The difference is left on the square substrate
1
a
as the margin
1
b.
The pressure applied to the punch
12
c
is dependent on the tensile strength of the insulating plate
1
. On the other hand, the smallest package is cut by using the punch
12
c
as narrow as 0.2 millimeter. However, such a thin punch
12
c
is liable to buckle in the punching due to the large pressure to be required for the glass fiber reinforced epoxy resin or the polyimide tape. If the manufacturer uses a wide punch
12
c
without increasing the area to be pinched, the plastic packages
4
tend to be damaged due to the pitching. Therefore, a fairly thick punch
12
c
and a wide area to be pinched are necessary for the prior art process, and the wide margin
1
b
is left on the square substrate
1
a
. The wide margin
1
b
makes the prior art semiconductor device large, and this is the first problem inherent in the prior art semiconductor device.
The second problem is the production cost. The glass fiber reinforced epoxy resin and the polyimide tape are expensive. As described hereinbefore, the wide margin
1
b
is indispensable, and the glass fiber reinforced epoxy resin or the polyimide tape for the margin
1
b
is wasteful. In other words, the manufacturer merely puts a small number of semiconductor chips
2
on a single sheet of the glass fiber reinforced epoxy resin or a single polyimide tape. This results in high production cost.
A solution is disclosed in Japanese Patent Publication of Unexamined Application No. 9-252065.
FIG. 2
illustrates the prior art semiconductor device disclosed in the Japanese Patent Publication of Unexamined Application. The prior art semiconductor device comprises an insulating frame
21
, a semiconductor chip
22
, ball bumps
23
and a plastic package
24
. A piece of glass fiber reinforced epoxy resin or a piece of polyimide tape is available for the insulating frame
21
. When the piece of polyimide tape is used as the insulating frame, it is cut from a long polyimide tape. Via holes
21
a
are formed in the insulating frame
21
, and a conductive pattern
21
b
is formed on a major surface and a reverse surface of the insulating frame
21
. The conductive pattern
21
b
is formed of copper. The conductive pattern
21
b
on the major surface is electrically connected to the conductive pattern
21
b
on the reverse surface through the via holes
21
a
. The conductive pattern
21
b
on the major surface is partially covered with an insulating layer
25
, and is exposed to holes
25
a
formed in the insulating layer
25
. The semiconductor chip
22
is bonded to the insulating layer
25
by means of adhesive compound
26
, and bonding pads
22
a
of the semiconductor chip
22
are connected through conductive wires
27
to the conductive pattern
21
b
exposed to the holes
25
a
, respectively. The conductive pattern
21
b
on the reverse surface is also partially converted with an insulating layer
28
, and is exposed to holes formed in the insulating layer
28
. The ball bumps
23
are bonded to the conductive pattern
21
b
exposed to the insulating layer
28
. The semiconductor chip
22
, the bonding wires
27
and a central area of the insulating layer
25
are scaled in the plastic package
24
.
Although the Japanese Patent Publication of Unexamined Application admits that the edges
24
a
of the plastic package
24
may be retracted from the side surfaces
21
c
of the insulating frame
21
by 0.1 millimeter or less, the Japanese Patent Publication of Unexamined Application asserts that the edges
24
a
are substantially aligned with the side surfaces
21
c.
A prior art process for fabricating the semiconductor device is described with reference to
FIGS. 3A-3F
. First, a printed circuit panel
31
is prepared as shown in FIG.
3
A. The conductive pattern
21
b
has been repeatedly printed on an insulating plate
31
a
of glass fiber reinforced epoxy resin or polyimide, and the conductive pattern
21
b
(not shown in
FIGS. 3A-3F
) as a whole constitute the printed circuit panel
31
. The circuit frame
21
a
/
21
b
is a part of the insulating plate
31
a.
The printed circuit panel
31
is placed on a die
32
. A punch
33
is pressed against the printed circuit panel
31
, and cuts the circuit frame
21
a
/
21
b
from the printed circuit panel
31
as shown in
FIG. 3B. A
scrap
31
Ise Hiroshi
Shironouchi Toshiaki
Hayes, Soloway, Hennessey Grossman & Hage, P.C.
NEC Corporation
Picardat Kevin M.
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