Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays
Reexamination Certificate
2001-04-10
2003-05-13
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
C438S693000, C438S700000, C438S701000, C438S728000, C438S732000, C430S005000
Reexamination Certificate
active
06563148
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device provided with a dummy pattern for alleviating irregularity of the surface due to an uneven density of a pattern being manufactured, and a method of placing such a dummy pattern.
2. Description of the Background Art
Conventionally, a semiconductor device has been known in which a dummy pattern is placed in an element isolating region so as to alleviate a problem of uneven or irregular surface of a separative insulating film, that is created in the element isolating region in chemical mechanical polishing (CMP) process due to sparseness of an originally designed element forming region pattern.
An example of dummy pattern being formed in an interconnection layer is disclosed in Japanese Patent Laying-Open No. 8-213396. An example of dummy pattern being formed with shallow trench isolation (STI) to separate element forming region patterns is disclosed in Japanese Patent Laying-Open No. 9-181159.
In recent semiconductor devices, STI has been utilized to separate all the elements therein, for simplification of manufacturing process. Thus, the element isolating region
103
as shown in
FIG. 18
has become extremely large.
Referring to
FIG. 18
, trenches
103
a
,
103
b
are formed in element isolating region
103
of a semiconductor substrate
101
, and an insulating film
102
is deposited to cover trenches
103
a
,
103
b
. Thereafter, CMP, etchback or the like is performed for planarization.
At this time, as shown in
FIG. 19
, a relatively large valley or depression is created on the surface of a separative insulating film
102
a
formed in the wide trench
103
a
as compared to the case of a separative insulating film
102
b
formed in the narrow trench
103
b.
A technique to prevent creation of such a large depression is to form, as shown in
FIG. 20
, a dummy pattern
105
in the wide trench
103
a
before deposition of insulating film
102
, CMP or the like.
According to this technique, as shown in
FIG. 21
, the depression of the surface of separative insulating film
102
a
left within the wide trench
103
a
after CMP or the like becomes less obvious. Thus, compared to the case where CMP or the like was performed without provision of dummy pattern
105
as in
FIG. 15
, it is possible to improve evenness or flatness of the surface of separative insulating film
102
a
formed within the wide trench
103
a
. Consequently, greater planarization of the semiconductor device is achieved.
To further improve planarization or dimension control of the semiconductor device, it is effective to reduce a pitch (width) of dummy pattern
105
. This enables dummy patterns
105
to be placed thoroughly over the entire semiconductor device, so that the planarization of the semiconductor device as well as the dimension control will further improve.
The conventional dummy patterns
105
, however, were placed automatically by calculation automatic design (CAD) process, and they had a fixed pitch. It was difficult to place such dummy patterns
105
with a fixed, small pitch thoroughly over the entire semiconductor device, because not only the CAD processing time but also the CAD processing capacity required would increase, and the processing itself might become impossible.
Placing the dummy patterns
105
uniformly over the entire semiconductor device poses another problem that dummy pattern
105
would be placed even in a region where the pattern density is originally large. In such a case, sufficient improvement in planarization cannot be expected.
SUMMARY OF THE INVENTION
The present invention is directed to solve the above-described problem. An object of the present invention is to improve the planarization of a semiconductor device, and, at the same time, to reduce the CAD processing time and capacity required for placement of dummy patterns.
The semiconductor device according to a first aspect of the present invention includes: an element pattern formed on a semiconductor substrate; a first dummy pattern placed in the same layer as the element pattern; and a second dummy pattern placed in the same layer as the element pattern and having a pitch different from that of the first dummy pattern. Herein, patterns in the “same layer” refer to layers or portions that exist in or on the semiconductor substrate approximately at the same height, like, e.g., neighboring dummy patterns
5
a
and
5
b
shown in FIG.
13
. The “element pattern” refers to a pattern constituting an element, which is a concept including an active area pattern, an interconnection pattern and the like, as will be described later in detail.
By providing the first and second dummy patterns having different pitches from each other, it is possible, e.g., to place the first dummy pattern having a relatively large pitch in a wide region of an element isolating region, and to place the second dummy pattern having a relatively small pitch in a relatively small region. Thus, the dummy patterns can be placed thoroughly over the entire semiconductor device. In addition, by placing the first and second dummy patterns according to pitch size, in descending order, for example, it is possible to substantially reduce a processing region for placement of the dummy pattern having the smaller pitch. As a result, compared to the case where dummy patterns with a fixed, small pitch are placed all over the regions, both the CAD processing time and the CAD processing capacity required can be reduced.
The element pattern may include an element forming region pattern (active area pattern) formed in the semiconductor substrate and isolated by an element isolating region. In this case, the first and second dummy patterns are placed in the element isolating region.
The element pattern may include an interconnection pattern formed on the semiconductor substrate. In this case, the first and second dummy patterns are placed around the interconnection pattern.
In either case, it is possible to place the dummy patterns thoroughly over the entire semiconductor device.
The semiconductor device according to a second aspect of the present invention includes: a plurality of mesh regions (divided regions) on a semiconductor substrate; an element pattern located within the mesh region; and a dummy pattern placed within the mesh region to occupy a certain ratio of an area therein determined according to an occupy ratio of the element pattern that is defined as a ratio of an area of the element pattern in the mesh region with respect to a total area of the mesh region.
Thus, by dividing the region on the semiconductor substrate into a plurality of mesh regions, and by placing the dummy pattern in each mesh region according to the occupy ratio of the element pattern therein, it becomes possible to appropriately place the dummy pattern in each mesh region according to the density of the element pattern therein. Thus, the dummy pattern can be placed thoroughly over the entire semiconductor device, and variation in degrees of irregularity among the mesh regions can be reduced. As a result, it is possible to improve the planarization of the semiconductor device. Further, by placing the dummy pattern of an appropriate size according to the density of the element pattern, the CAD processing time as well as the CAD processing capacity required can be reduced.
Preferably, the dummy pattern includes first and second dummy patterns having pitches different from each other. This helps further improve the planarization of the semiconductor device.
In either aspect, placement of the first dummy pattern and placement of the second dummy pattern are preferably carried out in different steps. In addition, if the semiconductor device has a first region in which the first dummy pattern is to be placed and a second region in which the second dummy pattern is to be placed, placement of the first dummy pattern in the first region and placement of the second dummy pattern in the second region are preferably carried out in separate steps. Further, it is preferable that the dummy
Igarashi Motoshige
Kawashima Hiroshi
Kitani Takeshi
Okada Masakazu
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Tran Mai-Huong
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