Semiconductor device with dummy pattern within active region...

Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Device protection

Reexamination Certificate

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Details

C257S202000, C257S355000, C257SE29014

Reexamination Certificate

active

08063412

ABSTRACT:
A semiconductor device includes a semiconductor substrate having an active region, a plurality of gate electrodes formed on the active region with a gate insulating film therebetween, and a dummy pattern formed on the active region in at least a part thereof between the gate electrodes. The dummy pattern is formed so that a spacing between gate electrodes adjacent to each other, and a spacing between the dummy pattern and the gate electrodes adjacent to the dummy pattern, are within predetermined ranges.

REFERENCES:
patent: 6835623 (2004-12-01), Shiau et al.
patent: 2009/0289284 (2009-11-01), Goh et al.
patent: 07-201858 (1995-08-01), None
patent: 08-236767 (1996-09-01), None
patent: 08-288295 (1996-11-01), None
patent: 10-200109 (1998-07-01), None
patent: 11-214634 (1999-08-01), None
patent: 2002-190589 (2002-07-01), None
patent: 2004-289138 (2004-10-01), None
patent: 2007-123442 (2007-05-01), None
patent: 2006-278952 (2009-11-01), None
Paul Grudowski et al.; 1-D and 2-D Geometry Effects in Uniaxially-Strained Dual Etch Stop Layer Stressor Integrations , 2006.
H. Tsuno et al.; Advanced Analysis and Modeling of MOSFET Characteristic Fluctuation Caused by Layout Variation, 2007.
Japanese Patent Office Action corresponding to Japanese Serial No. 2007-296295 dated Oct. 6, 2009.

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