Semiconductor device with dual damascene wirings and method...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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C257SE23010, C257SE21495, C257SE21579, C438S618000, C438S619000, C438S620000, C438S621000, C438S622000, C438S624000, C438S625000, C438S629000, C438S634000, C438S637000, C438S638000, C438S639000, C438S640000, C438S641000, C438S643000, C438S672000, C438S673000, C438S687000

Reexamination Certificate

active

08004087

ABSTRACT:
A multilayered wiring is formed in a prescribed area in an insulating film that is formed on a semiconductor substrate. Dual damascene wiring that is positioned on at least one layer of the multilayered wiring is composed of an alloy having copper as a principal component. The concentration of at least one metallic element contained in the alloy as an added component in vias of the dual damascene wiring is determined according to the differences in the width of the wiring of an upper layer where the vias are connected. Specifically, a larger wiring width in the upper layer corresponds to a higher concentration of at least one metallic element within the connected vias. Accordingly, increases in the resistance of the wiring are minimized, the incidence of stress-induced voids is reduced, and reliability can be improved.

REFERENCES:
patent: 6630741 (2003-10-01), Lopatin et al.
patent: 6979625 (2005-12-01), Woo et al.
patent: 2002/0024142 (2002-02-01), Sekiguchi
patent: 2004/0014312 (2004-01-01), Kunishima et al.
patent: 2004/0188850 (2004-09-01), Lee et al.
patent: 2005/0151266 (2005-07-01), Yoshizawa et al.
patent: 2005/0272258 (2005-12-01), Morita et al.
patent: 2006/0091551 (2006-05-01), Lin et al.
patent: 2009/0203208 (2009-08-01), Ueki et al.
patent: 9-289214 (1997-11-01), None
patent: 2000150522 (2000-05-01), None
patent: 2002-33384 (2002-01-01), None
patent: 2003-257970 (2003-09-01), None
patent: 2003-273209 (2003-09-01), None
patent: 2004-31847 (2004-01-01), None
patent: 2004-40022 (2004-02-01), None
patent: 2004-40101 (2004-02-01), None
patent: 2004-235620 (2004-08-01), None
patent: 2004-289008 (2004-10-01), None
patent: 2005-38999 (2005-02-01), None
International Search Report dated Oct. 25, 2005.
Kawano, M., et al., “Stress Relaxation in Dual-damascene Cu Interconnects to Suppress Stress-induced Voiding”, Proceedings of the IEEE 2003 International Interconnect Technology Conference, 2003, pp. 210-212.
Oshima, T., et al., “Improvement of Thermal Stability of Via Resistance in Dual Damascene Copper Interconnection”, IEEE International Electron Device Meeting, 2000, pp. 6.2.1-6.2.4.
Suzuki, T., et al., “Stress induced failure analysis by stress measurements in Copper dual damascene interconnects”, Proceedings of the IEEE 2002 International Interconnect Technology Conference, 2002, pp. 229-230.

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