Semiconductor device with DRAM and logic part integrated

Details Semiconductor device with DRAM and logic part integrated Semiconductor device with DRAM and logic part integrated

2000-12-08

2002-04-16

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Powering

C365S189011, C365S227000, C365S189110, C365S189050

Reexamination Certificate

active

06373773

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device in which a large capacity memory such as a DRAM (Dynamic Random Access Memory) and a logic IC such as a microcomputer, an ASIC (application specific integrated circuit), etc., are integrated into one chip.
2. Description of the Related Art
In recent years, as a high density and high integration for a semiconductor device have been demanded, a system LSI having a configuration in which a plurality of functional blocks are integrated into one chip has been developed. Recently, in particular, an LSI with embedded memory in which a large capacity memory such as a DRAM is mounted together with a logic IC on one chip has drawn considerable attention.
Furthermore, as power consumption in a semiconductor device has been reduced, accordingly, an LSI is operated with a low voltage power supply. Therefore, a block that cannot be operated with a low voltage power supply is operated by converting a signal with a low voltage operation level into a signal with a high voltage operation level by using a level shifter.
Hereinafter, a system configuration of a conventional DRAM will be described.
FIG. 6
is a diagram showing a system configuration of a conventional DRAM. In a semiconductor device
10
, numeral
3
denotes an input level shifter converting a DRAM control signal CL with a low voltage operation level, which is output from the logic part
2
, into a signal with a high voltage operation level. The DRAM control signal CH with a high voltage operation level, which is output from the input level shifter
3
, controls the DRAM
6
.
In the case wherein data is input, data as a signal DIOL with a low voltage operation level is input from an external input/output terminal
34
through a data input/output bus
13
to an input/output level shifter
12
and converted into a signal DIOH with a high voltage operation level in the input/output level shifter
12
; the converted signal is input through a data input/output bus
14
to an interface circuit
11
; and then the data as a data signal DIH is input from the interface circuit
11
through a data input bus
15
to the DRAM
6
.
On the other hand, in the case wherein data is output, data as a data signal DOH is output from the DRAM
6
through a data output bus
16
to the interface circuit
11
; is output from the interface circuit
11
as a data signal DIOH through the data input/output bus
14
to the input/output level shifter
12
and converted from the signal DIOH with a high voltage operation level into the signal DIOL with a low voltage operation level in the input/output level shifter
12
; and the converted signal is output to the external input/output terminal
34
.
FIG. 7
is a diagram showing a configuration of an input level shifter
3
of FIG.
6
. When a signal DRAMI with a low voltage operation level is input to a low voltage operation part
20
, the high voltage operation part
21
of the next stage outputs the signal DRAMO with a high voltage operation level without changing the logic of the DRAMI.
FIG. 8
is a diagram showing a configuration of an input/output level shifter
12
of FIG.
6
. Data input and data output are switched from each other by the level shifter control signal LSC (i.e. WREN, OECF). In this case, when the WREN is in a logic “H” level and the OECF is in a logic “L” level, the level shifter
12
is in a data input state. On the other hand, when the WREN is in a logic “L” level and the OECF is in a logic “H” level, the level shifter
12
is in a data output state.
Based on the above-mentioned flow of the DRAM control signal and data, a write operation and a read-out operation for the DRAM are performed.
However, in the conventional configuration, when the level shifter is used in order to reduce power consumption, the input/output level shifter
12
for converting the input/output signal from the low voltage operation level into the high voltage operation level or from the high voltage operation level into the low voltage operation level is required. The level shifter control signal LSC for selecting input or output is also required. Thus, the conventional circuit becomes complicated.
In addition, in the conventional configuration, both input data and output data are input/output signals. When the input/output signal is used as an input signal and output signal separately, it is necessary additionally to separate the input/output signal into an input signal and an output signal. Thus, another circuit is added.
SUMMARY OF THE INVENTION
It is an object of the present invention to simplify the circuit configuration by omitting an input/output level shifter and a level shifter control signal, and further to reduce power consumption.
Furthermore, it is another object of the present invention to make it easy to select separate I/O and shared I/O of a data input/output specification.
In order to achieve the above-mentioned objects, the present invention provides a semiconductor device in which a DRAM and a logic part are integrated into one chip: including an external input terminal for supplying the logic part with a signal necessary for the logic part to control the DRAM; an external data input terminal for supplying the logic part with input data; an external data output terminal for outputting the output data from the DRAM to the outside; a level shifter converting the operation voltage level of a DRAM control signal and the input data which are output from the logic part, and outputting the DRAM control signal to the DRAM; and an interface circuit controlling the input data output from the level shifter and the output data output from the DRAM by an interface control signal supplied from the DRAM, outputting the input data to the DRAM, and outputting the output data to the external data output terminal and the logic part. The logic part operates with a low voltage power supply.
With such a configuration, since the logic part can be operated at a low voltage by providing the input/output level shifter for both the DRAM control data signal and the input signal, it is possible to reduce the power consumption. Furthermore, since the input/output level shifter and the level shifter control signal for selecting an input data or output data are not required, it is not necessary to control the level shifter, thus simplifying the circuit.
It is preferable in the semiconductor device that the interface circuit includes a bit width changing part for changing the bit width in accordance with the bit width of the logic part by connecting neighboring data lines.
With such a configuration, in a bit width changing part of the interface circuit, neighboring data lines are connected to each other by a mask programmable option. Thus, the number of data lines can be reduced to ½ of the original number. Furthermore, four neighboring data lines are connected to each other by a mask programmable option, thus reducing the number of data lines to ¼ of the original number easily. Furthermore, by changing the configuration of the bit width changing part of the interface circuit, the number of data lines can be reduced further. Therefore, it is possible to realize a semiconductor device in which the bit width of the DRAM access can be changed easily in accordance with the bit width of the logic part.
Furthermore, it is preferable that the interface circuit includes a low voltage operation part for converting the output data signal from the DRAM into a signal with a low voltage operation level.
With such a configuration, in addition to the input/output level shifter, a data output low voltage operation part is provided on the interface circuit, and it is possible to reduce the consumption power by operating tri-state inverters with a low voltage power supply.
Furthermore, it is preferable that the interface circuit is programmable to select any one of separate I/O and I/O sharing for data input and data output.
With such a configuration, it is possible to realize easily a DRAM with separate I/O and shared I/O of

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