Semiconductor device with double moat and double channel stopper

Details Semiconductor device with double moat and double channel stopper Semiconductor device with double moat and double channel stopper

1980-04-07

1981-11-03

Clawson, Jr., Joseph E.

357 39, 357 50, 357 52, 357 55, 357 56, 357 86, H01L 2947

Patent

active

042988810

ABSTRACT:
This invention concerns a so-called double-moat uni-surface type semiconductor device in which two concentric moats are provided in one main surface of the substrate and the edges of the two pn-junctions for blocking main circuit voltages applied to the device are exposed in the surfaces of the moats. Semiconductor layers having high impurity concentrations and serving as channel stoppers are formed on the semiconductor layers exposed in the one main surface of the substrate, contiguous to the moats and spaced apart from the pn-junctions, each high impurity concentration layer having the same conductivity type as the semiconductor layer on which it is formed. The moats are filled with surface passivating material.

REFERENCES:
patent: 3911471 (1975-10-01), Kooi et al.
patent: 3918082 (1975-11-01), Hutson
patent: 4079403 (1978-03-01), Temple
patent: 4092703 (1978-05-01), Sueoka et al.
patent: 4148053 (1979-04-01), Bosselaar et al.
patent: 4156250 (1979-05-01), Trap

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