Semiconductor device with diffusion well isolation

Details Semiconductor device with diffusion well isolation Semiconductor device with diffusion well isolation

1992-07-06

1994-03-08

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

With pn junction isolation

257297, 257372, H01L 2702

Patent

active

052930602

ABSTRACT:
A semiconductor device has an upper well of a first conductivity type formed from the surface of an active region separated by an isolation oxide film at the surface of a semiconductor substrate to a predetermined depth. A first conductivity type layer of high concentration is formed along the entire region of an active region to enclose the bottom of the upper well of the first conductivity type. A lower well of the first conductivity type of a predetermined thickness is formed as a buried layer to enclose the bottom of the first conductivity type layer of high concentration. According to this structure, the spreadout of impurities into the active region due to diffusion at the time of thermal treatment is suppressed. The semiconductor device has the wells and the buried layer of high concentration formed by implanting impurities after the step of forming the isolation oxide film, so that diffusion of impurities into the active region due to thermal treatment at the time of isolation oxide film formation is suppressed. As a result, degradation of channel effect is prevented in miniaturization of the semiconductor device.

REFERENCES:
patent: 4424526 (1984-01-01), Dennard et al.
patent: 4633289 (1986-12-01), Chen
patent: 5019520 (1991-05-01), Komori et al.
patent: 5138420 (1992-08-01), Komori et al.
patent: 5148255 (1992-09-01), Nakazato et al.
Yamanaka et al., "A 25 .mu.m.sup.2, New Poly-Si PMOS Load (PPL) SRAM Cell Having Excellent Soft Error Immunity," IEEE IEDM 1988, pp. 48-51.
Kiyonori Ohyu et al., "Multilayered Well Formation for Sub-0.5 .mu.m CMOS Devices Utilizing High Energy Ion Implantation", Extended Abstracts of the 21st Conference on Solid State Devices and Materials, Tokyo, 1989, pp. 105-108.

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