Semiconductor device with delay locked loop

Details Semiconductor device with delay locked loop Semiconductor device with delay locked loop

1999-05-21

2001-04-17

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000

Reexamination Certificate

active

06218877

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor device, particularly to a semiconductor device provided with a delay locked loop (DLL) for phasing a signal inputted to or a signal outputted from the semiconductor device.
2. Description of the Related Art
There is a semiconductor device provided with a DLL circuit for phasing an input signal inputted from an outside of a semiconductor device, for example, an input clocked signal with an output signal which is outputted to the outside of the semiconductor device, for example, an output clock signal. The DLL circuit is provided with an internal delay reproduction circuit. The internal delay reproduction circuit reproduces delay time (hereinafter referred to as internal delay time) that is the sum of a delay time of a signal taken for inputting to the DLL circuit through an input pin via a pad or a buffer and a delay time of a signal taken for outputting from the DLL circuit through an output pin via the buffer or the pad. The internal delay time reproduced by the internal delay reproduction circuit is generally adjusted in advance by a metal option.
Since there occurs dispersion in process such as difference between rods and devices in mass production of semiconductor devices, there occurs the necessity to readjust the internal delay reproducing circuit. However, since the internal delay reproducing circuit is adjusted by a metal option in a conventional semiconductor device, it is very difficult to adjust or evaluate the internal delay reproducing circuit.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a new and improved semiconductor device provided with a DLL circuit capable of easily adjusting an internal delay time.
To achieve the above object, a semiconductor device according to an embodiment of the invention comprises an input terminal to which an input signal is inputted from the outside of the device, an output terminal from which an output signal is outputted to the outside of the device, and a phase adjusting circuit for phasing the input signal with the output signal, wherein the phase adjusting circuit comprises an internal delay reproduction circuit for reproducing the sum of a delay time of the input signal taken for inputting to the phase adjusting circuit and a delay time of the output signal taken for outputting from the phase adjusting circuit as the output signal, a delay adjusting circuit connected with the internal delay circuit upstream or downstream relative thereto for generating a given delay time for adjusting the internal delay time reproduced by the internal delay reproduction circuit, a delay time control section connected with the delay adjusting circuit for controlling the delay time generated by the delay adjusting circuit, a phase comparator for comparing a phase of a signal passed through the delay time adjusting circuit with a signal inputted to the phase adjusting circuit, and a delay selection circuit for generating a given delay time for allowing a phase of the signal passed through the delay adjusting circuit to coincide with a phase of the signal inputted to the phase adjusting circuit. The delay time control section comprises a plurality of fuse circuits including fuses so as to control the delay time generated by the delay adjusting circuit when fuses are burnt.
With such a construction, when the fuses are burnt, a delay time can be easily adjusted. There is another effect that devices which become failed caused by the difference in processes can be saved by adjusting the delay time by burning fuses when probing, and yield can be improved.
Further, the delay adjusting circuit may be provided with delay elements having the number that is less than one from the square of the number of fuse circuits. In this case, the delay elements may be formed of resistor elements. With such a construction, the number of resistor that is employed on the delay circuit may be changed to 2
n
possible numbers depending on whether respective fuses provided in n fuse circuits are burnt or not, and hence the delay time can be easily adjusted. When a delay generation section of the delay circuit is composed of resistors, there is no restraint on the layer to be achieved, thereby extending an area where a layout is provided.
Further, the delay elements may be formed of inverter elements. With such a construction, since each delay element is composed of each inverter, a layout can be achieved by a small space, and hence an influence by a wiring load can be reduced.
Still further, the delay time control section comprises a plurality of latch circuits wherein the delay time generated by the delay adjusting circuit may be controlled by external address information that is inputted to each latch circuit. With such a construction, the internal delay time can be easily controlled by inputting external address information. Further, since the delay time can be adjusted even after the delay adjusting circuit is incorporated into a mold, the evaluation including the influence of a package can be easily performed.
Further, the delay circuit may be provided with delay elements having the number less than one from the square of the latch circuits, wherein the delay elements may be formed of resistors. With such a construction, the number of resistors employed by the delay circuit can be changed by 2
n
by control n latch circuits, thereby easily adjusting the delay time. Further, the delay generation section of the delay circuit is composed of resistors, there is no limit in layers to be achieved, thereby extending an area where a layout is provided.
Still further, the delay elements are composed of even number of inverter elements. With such a construction, since the delay elements are composed of the inverter elements, a layout can be achieved by a small space and the influence by a wiring load can be reduced.


REFERENCES:
patent: 5087829 (1992-02-01), Ishibashi et al.
patent: 5994934 (1999-11-01), Yoshimura et al.
patent: 8-97714 (1996-04-01), None
patent: 8-130464 (1996-05-01), None
patent: 8-167890 (1996-06-01), None
patent: 8-274630 (1996-10-01), None
patent: 9-17179 (1997-01-01), None
patent: 10-39944 (1998-02-01), None

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