Semiconductor device with delay correction function

Details Semiconductor device with delay correction function Semiconductor device with delay correction function

2002-07-12

2004-04-13

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S261000, C375S371000

Reexamination Certificate

active

06720811

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device capable of adjusting a delay amount with high accuracy.
2. Description of Related Art
FIG. 12
is a schematic diagram illustrating a problem caused by the skew of a clock signal in conventional data transmission between two or more flip-flops.
FIG. 13A
is a timing chart illustrating a normal case, and
FIG. 13B
is a timing chart illustrating the problem.
In
FIG. 12
, the output of a flip-flop reaches the next flip-flop with a small amount of delay. For example, 5 ns delay occurs between Q and Q
1
in FIG.
12
. When the clock signals CK
1
and CK
2
to the two flip-flops change at perfectly uniform timing as illustrated in
FIG. 13A
, the output Q
2
of the second flip-flop changes one cycle after the output Q
1
of the first flip-flop.
In contrast, when the two clock pulses CK
1
and CK
2
change at different timings as illustrated in
FIG. 13B
, such as when the clock signal CK
2
delays 7 ns behind the clock signal CK
1
, that is, when the delay of the clock signal CK
2
is greater than the delay of data of 5 ns, the output Q
2
of the second flip-flop changes at nearly the same timing as the output Q
1
of the first flip-flop.
In such as case, various types of malfunctions can occur with the semiconductor device. For example, a timing signal can be generated at incorrect timing, a particular bit of a data signal composed of multiple bits can change its timing, and so forth.
Thus, the skew between the clock signals supplied to the flip-flops in the same clock signal domain can cause malfunctions in data latching or timing.
To eliminate the problem, such a design is made as the skew is retained below the data delay by means of the clock tree synthesis (CTS) or mesh clock signal generation. However, the CTS for all the flip-flops in an LSI in a large system is not always advantageous because of processing power of EDA (Electronic Design Automation) tools, or variations in the accuracy of the resultant skew. Thus, they are divided into a plurality of groups to carry out the CTS or mesh clock signal generation for individual groups.
In this case, however, the skew can occur between the clock signal domain groups. To adjust the inter-group skew, delay circuits for compensating for the skew are interposed at the roots of the respective groups in order to remove the inter-group skew involved in the transfer between the flip-flops.
FIG. 14
is a schematic diagram illustrating an arrangement for removing the skew by a conventional clock driver. To compensate for the skew between a group A with 3 ns delay and a group B with 7 ns delay, which delays are obtained as a result of the CTS, the clock driver assigns 5 ns delay to the group A and 1 ns delay to the group B, so that both the groups have 8 ns delay.
With such a skew eliminating method, however, the absolute value of the delay of the semiconductor device has great effect on the normal operation of the device. For example, if the 5 ns delay and 1 ns delay inserted are both doubled in an actual device, the total delays become 5×2+3=13 ns and 1×2+7=9 ns, respectively, thereby increasing the skew between the two clock pulse domains to 4 ns. Thus, the normal transfer between flip-flops becomes impossible.
If all the delays undergo the same effect, the delays in this case will be (5+3)×2=16 ns and (1+7)×2=16 ns, providing the same delay. However, the semiconductor device has various delay factors such as wiring, inter-layer capacitance, delay due to drain current Ids of transistors and so on. Accordingly, not all the delays are subjected to the same effect. As a result, a particular delay factor can bring about the skew.
FIG. 15
is a circuit diagram showing a configuration of a conventional nonoverlapping two-phase clock signal generating circuit, and
FIG. 16
is a timing chart illustrating conventional nonoverlapping two-phase clock signals.
To adjust the delay amount precisely in the conventional semiconductor device, the nonoverlapping two-phase clock signal generating circuit as shown in
FIGS. 15 and 16
is available, for example.
The two-phase clock signals are said to be nonoverlapping because they are never both in the high state at the same time. To utilize both the rising edge and falling edge of the two-phase clock signals, the width of the high state is sometimes controlled intentionally. In
FIGS. 15 and 16
, the high width of the clock signals are reduced to 5 ns using the inverter delays.
However, only connecting the inverters in series to utilize the delay of transistors can bring about unexpected delay when the difference increases between the delay based on the circuit simulation and the delay of actual device, thereby causing malfunctions.
For example, it is very difficult for the delays connected in series to implement the clock signal width of 5-7 ns with the nonoverlapping width of 1 ns. This is because the delays connected in series are subjected to the manufacturing variations of the semiconductor device, and hence they can hardly carry out the highly accurate control of the width of the clock signal.
Furthermore, it is often necessary for the semiconductor device to generate clock signals with their phase aligned in a system that includes a first clock signal and a second clock signal with different phases, the first clock signal having a specified period and the second clock signal having the period identical to or integer multiple of the period of the first clock signal.
However, it is not easy to generate the clock signals with their phased synchronized.
With the foregoing configuration, the conventional semiconductor device cannot adequately remove the delay error caused by the manufacturing variations of the semiconductor device by the method as shown in
FIG. 14
that tries to eliminate the skew using the clock driver. Thus, it has a problem of impairing the normal operation.
In addition, the nonoverlapping two-phase clock signal generating circuit as shown in
FIG. 15
has a problem of causing the delay error due to the manufacturing variations in the semiconductor device, thereby hindering the normal operation.
Furthermore, it is difficult for the system, which includes the first clock signal with the specified period, and the second clock signal with the period identical to or integer multiple of the period of the primary clock signal and with different phases, to generate the clock signals with aligned phases.
SUMMARY OF THE INVENTION
The present invention is implemented to solve the foregoing problems. It is therefore an object of the present invention to provide a semiconductor device capable of eliminating the delay error caused by the manufacturing variations, thereby correcting the delay to a desired delay amount.
Another object of the present invention is to provide a semiconductor device capable of generating a clock signal with a period identical to or integer multiple of the period of an input clock signal, and with its phase aligned to the input clock signal.
According to a first aspect of the present invention, there is provided a semiconductor device comprising: delay amount measuring means for measuring an actual delay amount corresponding to a specified delay amount by supplying a clock signal with a known period to a plurality of delay strings, each of which has a delay amount determined in advance; a plurality of delay sections each including a delay string capable of freely adjusting a connection number of its delay elements; and correction signal generating means for generating a correction signal for enabling each of the delay sections to correct the connection number of the delay strings such that each delay section has a desired delay amount in accordance with the actual delay amount. Thus, it offers an advantage that the delay measuring means can detect the delay error due to the manufacturing variations of the semiconductor device after the fabrication, and that the correction signal generati

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