Semiconductor device with data line arrangement for preventing n

Details Semiconductor device with data line arrangement for preventing n Semiconductor device with data line arrangement for preventing n

1999-02-17

2000-08-22

Nguyen, Tan T.

Static information storage and retrieval

Interconnection arrangements

365 69, G11C 506

Patent

active

061082309

ABSTRACT:
A semiconductor memory device having a data line structure is disclosed which is capable of eliminating a noise interference between data lines and enhancing an integrity of a memory device. In the semiconductor memory device, a pair of data lines are not aligned on the identical plane. Namely, it is separated into an upper layer line and a lower layer line using an insulation film, wherein the data lines forming a plurality of pairs of the data lines are aligned in the upper wiring line and lower wiring line on a semiconductor substrate, and have at least one intersected portion therebetween.

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patent: 5602772 (1997-02-01), Nakano et al.
patent: 5602773 (1997-02-01), Campbell

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