Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
2001-05-16
2003-01-21
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C257S021000, C257S027000, C257S183000, C257S184000, C257S187000, C257S196000, C442S417000, C442S417000, C442S417000, C442S417000, C442S417000
Reexamination Certificate
active
06509580
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device with one or more current confinement regions and to a method of manufacturing such a device, particularly buried heterostructure light emitting devices such as semiconductor lasers and light emitting diodes.
2. Description of the Prior Art
Buried heterostructure light emitting devices commonly have current confinement regions defined by areas of high resistivity that channel current to an optically active layer within the structure. In devices using InGaAsP/InP materials, current confinement regions have been employed based on a reverse-biased p-n or n-p diode structure. Such structures provide high resistivity, and low leakage currents, and are widely used in fibre optic communication systems across a range of operating frequencies. At operating frequencies about 1 GHz, however, the performance of such devices becomes limited by the capacitance of the current blocking structure, owing to the charge on the reverse biased diode junction.
Other current blocking structures have therefore been developed, for example Fe-doped InP-based layers, as described in U.S. Pat. No. 4,660,208. Such Fe-doped layers have a lower capacitance than structures based on a reverse biased junction, but do not have as high a resistivity. This lower resistivity also limits operation and device lifetime at high frequencies, because of the resulting higher device operating temperatures. In order to avoid excessive temperatures, it becomes necessary to use a lower drive voltage, and this in turn limits the achievable bandwidth of a device based on Fe-doped material.
SUMMARY OF THE INVENTION
In recent years there has been an increasing demand for fibre optic communication links having a bandwidth in excess of 1 GHz, for example up to 10 GHz. It is an object of the present invention to provide a semiconductor device that addresses these issues.
Accordingly, the invention provides a semiconductor device comprising an active layer, a current conduction region, one or more current confinement regions adjacent the current conduction region, the current conduction region and current confinement region being arranged to channel electric current to the active layer, wherein the or each current confinement region includes both a metal-doped current blocking structure and a p-n junction current blocking structure, the p-n current blocking structure being between the current conduction region and the metal-doped current blocking structure.
It has been found that the p-n current blocking structure nearest the current conduction region then provides high resistivity and good high frequency performance at high temperatures, while the reduction in the volume of the p-n current blocking structure and use of the metal-doped second current blocking structure further away from the current conduction region provides reduced parasitic capacitance.
In some type of device, for example buried heterostructure laser diodes, the device includes a substrate, a mesa stripe on the substrate and an active layer in the mesa stripe. The current conduction region then channels current through the active layer.
The mesa stripe may have one or more side walls that rise above the substrate. The active layer then extends to the side wall(s) and the active layer is covered at the side walls by the p-n blocking structure.
In preferred embodiments of the invention, the mesa side walls slope laterally away from the active layer towards the metal-doped current confinement structure. Also in a preferred embodiment, the metal-doped current confinement structure abuts the p-n current confinement structure along a substantially vertical interface.
Also according to the invention, there is provided a method of forming semiconductor device comprising an active layer, a current conduction region, one or more current confinement regions adjacent the current conduction region, the current conduction region and current confinement region being arranged to channel electric current to the active layer, wherein the method comprises the steps of:
i) growing upon a semiconductor substrate a plurality of semiconductor layers, including the active layer and the current conduction region by which electric current may be applied to the active layer;
ii) growing adjacent the active layer a p-n junction current blocking structure; and
iii) growing adjacent the p-n junction current blocking structure a metal-doped current blocking structure, the p-n-junction current blocking structure and the metal-doped current blocking structure together forming a current confinement region for channelling electric current to the current conduction region.
In one embodiment of the invention, prior to step ii), a first etch mask is formed over the active layer, said first etch mask defining during an etching process an area of the active layer adjacent the current conduction region to be removed by the etching. Then, prior to step iii) a second etch mask is formed over the active layer and the p-n junction current blocking structure adjacent the current conduction region, said second etch mask defining during an etching process an area of p-n junction current blocking structure not adjacent the active layer to be removed by the etching.
This second etch mask may then remain in place during the growth of the metal-doped current blocking structure in step iii).
In order to achieve a sufficiently uniform width of the first current blocking structure, the second etch mask is then aligned laterally with the first etch mask, typically to an accuracy of about 10% to 20% of the width of the second etch mask. In one preferred embodiment of the invention, the second etch mask is laterally wider than the first etch mask.
In another embodiment of the invention, prior to step ii), an etch mask is formed over the active layer, said etch mask defining during a first etching process an area of the active layer adjacent the current conduction region to be removed by the etching. The etch mask remains during the growth of the p-n current blocking structure in step ii). Finally, the etch mask defines during a second etching process an area of the p-n junction current blocking structure not adjacent the active layer to be removed by the etching.
This etch mask may then remain in place during the growth of the metal-doped current blocking structure in step iii).
Because this process uses only one mask for the formation of the first current conduction structure and the second current conduction structure, the process is self-aligning for these two current blocking structures.
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van der Linden, J.E., Examiner. European Search Report, Application No. EP 01 30 0447, dated Jun. 25, 2001.
Agilent Technologie,s Inc.
Meier Stephen D.
Soward Ida M.
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