Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1998-10-07
2001-06-05
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S751000, C257S767000, C438S687000
Reexamination Certificate
active
06242808
ABSTRACT:
This application is based on Japanese Patent Application No. 10-97948 filed on Apr. 9, 1998, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a)Field of the Invention
The present invention relates to a semiconductor device with a Cu wiring and a method for manufacturing the semiconductor device.
b)Description of the Related Art
With the recent improvements in the processing techniques utilized for semiconductor large-scale integration (LSI), the high-density arrangement of wires and the employment of a multilayer structure and thin film technology in forming a wiring have been promoted, as well as the miniaturization of individual elements. The stress applied to the wires and the density of the current flowing through the wires have increased accordingly. When considering typical logic LSI, for example, the density of the current made to flow through a power supply wire is approximately 1×10
5
A/cm
2
in the case of LSI under the 0.35 &mgr;m design rule, while the density of the current in the case of LSI under the 0.25 &mgr;m design rule is higher, i.e., 3×10
5
A/cm
2
. In the case of LSI under the 0.18 &mgr;m design rule, the density of the current is 1×10
6
A/cm
2
. An increase in the density of the current entails a problem of the wiring breakage owing to electromigration.
Conventionally, aluminum (Al) has been employed as the material of a wiring in LSI. The ability of an Al wiring to withstand electromigration is improved by adding an impurity such as Cu, Si, Ti, Pd or the like to Al or by adopting a stacked structure which is composed of an Al wiring layer and metal layers, between which the Al wiring layer is sandwiched and which are made of metals having high melting points, such as TiN, Ti, TiW, etc.
However, there is a limit to the use of the Al wiring, due to a signal transmission delay depending upon the resistivity of Al and limitations on the density of a current which can be made to flow through the Al wiring.
Cu has received attention as a wiring material which can be substituted for Al. The resistivity of Cu is lower by approximately 37% than that of Al, and a signal transmission delay owing to electric resistance is lower accordingly. Cu, if employed, can increase the density of a current, which can be made to flow through a wiring, up to about ten times that in the case of Al. This is because the melting point and the self-diffusing energy of Cu are higher than those of Al.
Cu is a material which is difficult to finely process with dry etching techniques, and it is therefore difficult to form a Cu wiring with the processing techniques which have been conventionally used to form an Al wiring. In consideration of this, a damascene process of forming a wiring groove in an interlayer insulation film and filling the groove with Cu has received attention. In the case of forming a Cu wiring with the damascene process, it is required to completely fill a via hole and a groove which have a high aspect ratio. Known as such filling processes are a sputtering process, a plating process and a chemical vapor deposition (CVD) process.
In the sputtering process, a Cu film is deposited by sputtering, after which a heat treatment is conducted at 350° C. or higher, thus filling a via hole and a groove with Cu. With the sputtering process, however, it is difficult to completely fill a groove having a high aspect ratio. The approximate aspect ratio of such a groove as can be filled completely is between 1 and 1.5 at most.
In the CVD process, a groove having a high aspect ratio can be filled completely. Generally speaking, however, film growth in the CVD process is slow. This would result in a low throughput and a high manufacturing cost.
In the plating process, a groove is filled by plating Cu. According to electro-plating, a groove having a high aspect ratio can be filled completely, since Cu ions contained in a plating solution can be led up to the bottom of the groove. The film formation speed is relatively high, and therefore the plating process is suitable for use in mass production.
However, the plating process is a wet process. With such a wet process, it would be difficult to form a high-quality Cu film having an excellent ability to endure electromigration. Moreover, the adhesion of the film to the underlying surface would be low.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to provide a semiconductor device with a Cu wiring whose adhesion to the underlying surface is high and which has an excellent electromigration resistance.
It is another object of the present invention to provide a method for forming, by plating, a Cu wiring whose adhesion to the underlying surface is high and which has an excellent electromigration resistance.
According to one aspect of the present invention, there is provided a semiconductor device which comprises a substrate, having an insulative surface, and a wiring formed on the substrate; wherein the wiring has a stacked structure including a barrier layer and a Cu layer, the barrier layer is made of a material which prevents Cu atoms contained in the Cu layer from diffusing into the substrate, a precipitated impurity is present at an interface between the barrier layer and the Cu layer, the Cu layer contains the same impurity as the precipitated impurity present at the interface, the impurity concentration at a certain region of the Cu layer being lower, the farther the certain region being from the interface between the Cu layer and the barrier layer.
The precipitated impurity present on the interface between the barrier layer and the Cu layer ensures the improved adhesion of the Cu layer to the barrier layer. The impurity contained in the Cu layer, which impurity is the same as that precipitated on the interface, improves the electromigration resistance of the Cu layer. The farther from the interface between the Cu layer and the barrier layer, the lower impurity concentration of the Cu layer. This enables a decrease in the electric resistance of the Cu layer to be suppressed.
According to another aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: an insulation film deposition step of depositing an interlayer insulation film on a substrate in which a semiconductor element has been formed; a groove formation step of forming a wiring groove in the interlayer insulation film; a barrier layer deposition step of depositing a barrier layer, made of a material which prevents a diffusion of Cu atoms, on an inner surface of the wiring groove and an upper surface of the interlayer insulation film; a seed layer deposition step of depositing, on the barrier layer, a seed layer essentially consisting of Cu which contains an impurity; a conductive layer deposition step of depositing, by plating, a conductive layer consisting of Cu on the seed layer so as to fill the wiring groove; a precipitation step of precipitating the impurity, contained in the seed layer, on at least an interface between the seed layer and the barrier layer by heating the substrate; and a surface planarization step of removing parts of the conductive layer, the seed layer and the barrier layer until the upper surface of the interlayer insulation film appears.
According to another aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: an insulation film deposition step of depositing an interlayer insulation film on a substrate in which a semiconductor element has been formed; a groove formation step of forming a wiring groove in the interlayer insulation film; a barrier layer deposition step of depositing a barrier layer, made of a material which prevents a diffusion of Cu atoms, on an inner surface of the wiring groove and an upper surface of the interlayer insulation film; a stacked structure formation step of forming, on the barrier layer, a stacked structure which includes an impurity layer, consisting of one of a metal and a semiconductor, and a seed layer consisting of Cu
Kitada Hideki
Ohtsuka Nobuyuki
Shimizu Noriyoshi
Armstrong, Westerman Hattori, McLeland & Naughton
Chaudhuri Olik
Fujitsu Limited
Peralta Ginette
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