Semiconductor device with connecting via and dummy via and...

Details Semiconductor device with connecting via and dummy via and... Semiconductor device with connecting via and dummy via and...

2005-05-25

2008-08-26

Nguyen, Thanh (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S758000, C257SE21577

Reexamination Certificate

active

07417319

ABSTRACT:
An underlying interconnect including a first barrier metal layer, an interconnect metal layer and a second barrier metal layer is formed on a semiconductor substrate, and an interlayer dielectric is formed thereon. Etching is performed with a photoresist defining an opening for a first via, and an opening for a second via having a larger bottom area than the first via opening, so as to form a first via hole and a second via hole in the interlayer dielectric. Since the second via hole has a larger diameter than the second via hole, the second via hole is opened up prior to the second via hole, and the underlying interconnect is exposed first at the bottom of the second via hole.

REFERENCES:
patent: 5793113 (1998-08-01), Oda
patent: 6153510 (2000-11-01), Ishibashi
patent: 6287948 (2001-09-01), Ushiyama
patent: 2003/0211716 (2003-11-01), Segawa
patent: 2004/0152256 (2004-08-01), Noguchi et al.
patent: 1459842 (2003-12-01), None
patent: 2003-218199 (2003-07-01), None
patent: 2004-134610 (2004-04-01), None

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