Semiconductor device with conductive contact layer structure

Details Semiconductor device with conductive contact layer structure Semiconductor device with conductive contact layer structure

1996-10-07

2004-05-04

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S296000, C257S772000, C257S773000

Reexamination Certificate

active

06731008

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to a conductive layer contact structure for a conductive region formed at the surface of a semiconductor substrate between the conductive layers formed on the semiconductor substrate and a method of manufacturing the same.
2. Description of the Background Art
Recently, as can be seen from the fact that DRAMs (Dynamic Random Access Memories) and the like are becoming integrated to a higher degree, degree of integration of semiconductor devices is being made higher, and thus dimension of the diameters of the contact holes is becoming more and more reduced as a result of increase in degree of integration of the elements incorporated into the semiconductor devices. In order to form a smaller contact hole, polycrystalline silicon mask opening method and self align contact (SAC) opening method are being considered.
FIG. 26
is a partial cross sectional view of a semiconductor device, showing a contact hole formed by polycrystalline silicon mask opening method at a memory device region of a semiconductor device. Referring to
FIG. 26
, an isolation oxide film
2
is formed at the surface of a p type polycrystalline silicon substrate
1
by the method of LOCOS (Local Oxidation of Silicon). On the surfaces of p type silicon substrate
1
and isolation oxide film
2
, gate oxide films
3
are formed. A gate electrode
4
is formed on this gate oxide film
3
. An insulation film
5
is formed on gate electrode
4
. On the surface of p type silicon substrate
1
at both sides of gate electrode
4
, n
−
diffused regions
6
containing an n type impurity of low concentration are formed by the method of LDD (Lightly Doped Drain). At the side surfaces of gate oxide film
3
, gate electrode
4
and insulation film
5
, sidewall spacers
7
are formed as insulation films. In addition, an n
+
diffused layer
8
containing n type impurity of high concentration is formed at the surface of p type silicon substrate
1
so as to join n
−
diffused regions
6
. Covering gate electrode
4
, an interlayer insulation film
11
of silicon oxide film is formed on the surface of p type silicon substrate
1
, employing TEOS (Tetraethyl Orthosilicate) as the material. In this interlayer insulation film
11
, a contact hole
105
of a small diameter is formed by etching interlayer insulation film
11
to reach a portion of the surface of n
+
diffused layer
8
.
Description will be made for a method of forming the contact hole shown in
FIG. 26
, with reference to
FIGS. 27A
to
27
B and
27
B to
30
B.
FIGS. 27A
to
30
A are partial cross sectional views illustrating the process of forming the contact hole shown in
FIG. 26
at the memory device region in the order of the steps performed.
FIGS. 27B
to
30
B are partial cross sectional views illustrating the process of forming the contact hole shown in
FIG. 26
at the peripheral circuit region in the order of the steps performed.
Referring to FIGS.
27
A and
FIG. 27B
, isolating oxide film
2
, gate oxide film
3
, gate electrode
4
, insulation film
5
, n
−
diffused layer
6
, sidewall spacer
7
, n
+
diffused layer
8
and interlayer insulation film
11
having a thickness of 3000 to 4000 Å are formed on p type silicon substrate
1
. Thereafter, a polycrystalline silicon film
101
having a thickness of 1500 to 3000 Å is deposited on the entire surface of the interlayer insulation film, and a silicon oxide film
102
employing TEOS as its material (hereinafter referred to as “TEOS oxide film”) is further deposited thereon. On this TEOS oxide film
102
, a resist (not shown) is formed, and using the patterned resist as a mask, TEOS oxide film
102
is partially etched. Thus, a hole
103
a
having a diameter of about 0.3 &mgr;m is formed to reach the surface of polycrystalline silicon film
101
. Then, on the entire surface of TEOS oxide film
102
, a TEOS oxide film is deposited again. By etching back the entire surface of this TEOS oxide film with anisotropical etching, a sidewall spacer
103
of TEOS oxide film is formed at the inner sidewall of hole
103
a
which had been formed at TEOS oxide film
102
.
Thereafter, as shown in
FIGS. 28A and 28B
, polycrystalline silicon film
101
is etched using TEOS oxide film
102
and sidewall spacer
103
as a mask so as to form a hole
104
having a diameter of 0.08 to 0.12 &mgr;m. Then, TEOS oxide film
102
and sidewall spacer
103
are etched away.
Then, referring to
FIGS. 29A and 29B
, polycrystalline silicon film
101
is used as a mask to etch interlayer insulation layer
11
thereby forming a contact hole
105
with a small diameter. Thereafter, as shown in
FIGS. 30A and 30B
, polycrystalline silicon film
101
is removed by having its surface entirely subjected to etching. Thus, the contact hole shown in
FIG. 26
is formed.
When forming a contact hole with polycrystalline silicon mask opening method as described above, there has been the following problems. First of all, when a contact hole of a small diameter having a high aspect ratio, for example, not lower than 4, is formed at interlayer insulation layer
11
, the etching rate would be extremely low, and thus it was very difficult to open a contact hole by an accurate etching. In addition, since it is difficult to bury the material of the conductive layer inside the contact hole after the contact hole is formed, it was difficult to form a conductive layer along the inner sidewall of the contact hole such that a satisfactory step coverage is obtained. Accordingly, there has been problems such as disconnection of conductive layer
106
and increase in contact resistance between conductive layer
106
and n
+
diffused layer
8
, as shown in FIG.
31
.
Moreover, in the case of forming a contact hole with polycrystalline silicon mask opening method, when etching back the entire surface of polycrystalline silicon film
101
, there has been a problem that etching is performed at the peripheral circuit region until the surface of gate electrode
4
is exposed, as shown in FIG.
30
B. This is because the thickness of interlayer insulation layer
11
covering the surface of gate electrode
4
is thin due to the wide interval between the gate electrodes.
FIG. 32
is a partial cross sectional view showing a semiconductor device having a contact hole formed by self align contact opening method. Referring to
FIG. 32
, a gate oxide film
3
is formed on the surface of a p type silicon substrate
1
. A gate electrode
4
is formed on gate oxide film
3
. An insulation film
5
is formed on gate electrode
4
. N
−
diffused regions
6
are formed at the surface of p type silicon substrate
1
at both sides of gate electrode
4
by the method of LDD. Sidewall spacer
7
is formed at the side surface of gate oxide film
3
, gate electrode
4
and insulation film
5
. N
+
diffused regions
8
are formed at the surface of p type silicon substrate
1
so as to join n
−
diffused layers
6
. Silicon oxide film
9
is formed on the surface of p type silicon substrate
1
covering insulation film
5
and sidewall spacer
7
. A silicon nitride film
10
is formed on silicon oxide film
9
.
Moreover, an interlayer insulation layer
11
of TEOS oxide film is formed on silicon nitride film
10
. Contact hole
110
is formed to penetrate silicon oxide film
9
, silicon nitride film
10
and interlayer insulation layer
11
to reach a portion of the surface of n
+
diffused layer
8
. A polycrystalline silicon layer
17
and a tungsten silicide layer
18
are formed as a conductive layer for being in electrical connection with n
+
diffused layer
8
via contact hole
110
. This conductive layer has two-layered structure including polycrystalline silicon
17
and tungsten silicide
18
to reduce interconnection resistance.
Referring next to
FIGS. 33
to
36
, description is made for a method of forming the contact hole of FIG

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