Semiconductor device with clad substrate and fabrication process

Details Semiconductor device with clad substrate and fabrication process Semiconductor device with clad substrate and fabrication process

1994-12-15

1996-06-25

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 57, 437 59, 437 72, H01L 21302, H01L 21304, H01L 21306, H01L 2176

Patent

active

055299474

ABSTRACT:
On a first surface of a first single crystal silicon substrate, in which a silicon dioxide layer having gradually tapered peripheral edge (tapered wall), a second single crystal silicon substrate is clad. On the second surface of the first single crystal silicon substrate, an island form polycrystalline silicon region is isolated from remaining region by an isolation groove to form an element. By reducing step between the buried silicon dioxide layer and the first single crystal silicon substrate, local concentration of a stress can be successfully avoided. Also, abrasion of the silicon oxide layer and single crystal silicon substrate having mutually different etching speeds is not performed so that the step can be lowered to eliminate formation of void. Between the first surface of the first single crystal silicon substrate formed with the elements and the cladding surface, the silicon dioxide layer is present to avoid influence of contaminant penetrating during cladding process. Accordingly, degradation of reliability due to stress concentration and formation of void, and contamination in the SOI clad substrate can be successfully avoided.

REFERENCES:
patent: 4837186 (1989-06-01), Ohata et al.
patent: 4963505 (1990-10-01), Fujii et al.
patent: 5223450 (1993-06-01), Fujino et al.
patent: 5350492 (1994-09-01), Hall et al.
patent: 5356827 (1994-10-01), Ohoka
patent: 5403769 (1995-04-01), Fujii

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