Amplifiers – With semiconductor amplifying device – Including temperature compensation means
Reexamination Certificate
2001-07-11
2004-03-16
Lam, Tuan T. (Department: 2816)
Amplifiers
With semiconductor amplifying device
Including temperature compensation means
C330S129000, C330S133000
Reexamination Certificate
active
06707341
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor devices and particularly to those including a bipolar transistor device configured of transistor cells arranged in a matrix.
2. Description of the Background Art
Power amplifiers for mobile communications currently, widely used include monolithic microwave integrated circuits (MMICs), hybrid integrated circuits (hybrid ICs), multitip modules and the like. These modules have an amplifying element in the form of a GaAs-metal semiconductor field effect transistor (GaAs-MESFET), a high electron mobility transistor (HEMT), a hetero-junction bipolar transistor (HBT) or the like.
Particularly, a hetero-junction bipolar transistor (hereinafter also simply referred to as an HBT) formed on a GaAs substrate, a Si substrate or the like is expected to serve as a future power element for mobile communications as it is more advantageous than conventional field effect transistors (FETs), as described below:
(1) operable by a single power supply as it does not require a negative gate bias voltage;
(2) capable of turning on/off without having an analogue switch on its drain side, as in a Si-metal oxide semiconductor FET (Si-MOSFET); and
(3) having a high output power density, thus capable of providing a defined output if it is reduced in size as compared to FET power amplifiers.
As such features of the HBT attract attention, an HBT power amplifier is also being applied for example to a 2 W-4 W, high-output mobile telephone, such as the European Global System for Mobile Communications (European GSM), a currently most widely used, 900 MHz band mobile telephone system mainly employing a Si-MOSFET.
A power amplifier employs a transistor device generally configured of a plurality of transistor cells arranged on a semiconductor substrate in rows and columns. Hereinafter such a configuration will also be referred to as a multi transistor cell configuration.
FIG. 14
is a circuit diagram showing a configuration of a bipolar transistor device having a multi transistor cell configuration.
With reference to
FIG. 14
, a plurality of transistor cells Tr
11
-Trmn arranged in m rows and n columns in effect operate as a single bipolar transistor device TR, wherein m and n are each a natural number.
Corresponding to the rows of transistor cells, local base lines LBL
1
-LBLm and local collector lines LCL
1
-LCLm are arranged, respectively. Hereinafter, local base lines LBL
1
-LBLm and local collector lines LCL
1
-LCLm will generally be referred to as a local base line LBL and a local collector line LCL, respectively.
Each transistor cell has its base and collector regions electrically coupled with its corresponding row's local base and collector lines LBL and LCL, respectively.
Local base lines LBL
1
-LBLm are each electrically coupled with a common base line CBL. On common base line CBL, a bias current Ibs supplied from a bias supply circuit (not shown) is superimposed on an RF signal input to a base terminal Tb.
Local collector lines LCL
1
-LCLm are each electrically coupled with a common collector line CCL. Furthermore, each transistor cell has its emitter region electrically coupled with a ground voltage Vss to provide a so-called emitter-grounding.
Transistor device TR applied to a power amplifier receives a radio-frequency input (an RF signal input) at base terminal Tb coupled with common base line CBL and outputs an amplified, radio-frequency output (RF signal output) at collector terminal Tc coupled with common collector line CCL.
Corresponding to transistor cells Tr
11
-Trmn, base ballast resistors Rb
11
-Rbmn and emitter ballast resistors Re
11
-Remn are provided, respectively. A ballast resistor is generally used to prevent a bipolar transistor device having a multi transistor cell configuration from having an uneven collector current attributable for example to an uneven heat distribution caused by heat generation.
More specifically, each base ballast resistor and each emitter ballast resistor when their respective transistor cell operates give a negative feedback to a base current and an emitter current, respectively. Thus they act to eliminate a variation in current between transistor cells to provide a uniform current. This can prevent a specific transistor cell from intensively receiving current and thus prevent the transistor from being thermally destroyed.
FIG. 15
is a conceptual view showing a layout of a bipolar transistor device having a multi transistor cell configuration.
FIG. 15
shows a bipolar transistor device TR configured of transistor cells Tr
11
-Tr
67
arranged in six rows and seven columns by way of example. Transistor cells Tr
11
-Tr
67
are grouped into blocks BLK
1
-BLK
3
each formed of two rows of transistor cells.
Corresponding to blocks BLK
1
-BLK
3
, local base lines LBL
1
-LBL
3
are arranged, respectively. Each transistor cell has its base region electrically coupled with its corresponding local base line LBL via a base ballast resistor. In
FIG. 15
, the arrangement of a base ballast resistor Rb
12
for transistor cell Tr
12
is shown representatively.
Local base lines LBL
1
-LBL
3
are each coupled with common base line CBL. Common base line CBL passes bias current Ibs and also receives an RF signal input.
Each transistor cell has its collector region coupled with a respective one of local collector lines LCL
1
a
and LCL
1
b
to LCL
3
a
and LCL
3
b
provided for their respective rows of transistor cells. Local collector lines LCL
1
a
and LCL
1
b
to LCL
3
a
and LCL
3
b
are each coupled with collector terminal Tc outputting an amplified RF signal.
Similarly, each transistor cell has its emitter region electrically coupled via an emitter ballast resistor (not shown) with common emitter line CEL coupled with ground voltage Vss.
FIGS. 16A and 16B
are graphs each showing a distribution of a base current in a bipolar transistor device having a multi transistor cell configuration.
With reference to
FIG. 16A
, if the
FIG. 15
bipolar transistor TR has a small base current, thermal, mutual interference between the blocks and that between the transistor cells only have a small effect and blocks BLK
1
-BLK
3
have their respective base currents Ib
1
-Ib
3
that are substantially uniform and thus provide a standard amount of current I
1
.
In contrast, as shown in
FIG. 16B
, if base current in total increases and thermal, mutual interference between the blocks and that between the transistor cells are no longer negligible, the operating temperature of transistor cells closer to the center of the transistor increases higher than that of peripheral transistor cells and the transistor cells with their operating temperature increased thus have an increased collector current.
In the
FIG. 15
exemplary layout, base current Ib
2
for block BLK
2
closer to the center and thus greater in temperature elevation would have an amount of current I
3
(wherein I
3
>>I
1
) larger than an amount of current I
2
of base currents Ib
1
and Ib
3
for the other blocks (wherein I
2
<I
1
). Thus a specific block receives an intensive current.
Furthermore even within a single block a transistor cell closer to the center of the block has its operating temperature increased, resulting in a further uneven temperature profile. For example in
FIG. 15
transistor cells Tr
34
and Tr
44
would have an operating temperature that most readily increase.
Thus, an uneven operating-temperature profile results in an uneven base current (or an uneven collector current), which in turn results in an unevenness between the blocks and further develops to a current intensively flowing in a block through a specific transistor cell, and ultimately, approximately more than 90% of the base current (collector current) flowing through the entire transistor device TR would intensively flow to the specific transistor cell.
Such a significantly intensive current results in the transistor cell having a current-amplification rate &bgr; (collector current/base current) significantly reduced due to
Suzuki Satoshi
Yamamoto Kazuya
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